Abstract: Methods, systems, and apparatuses are disclosed for a computer-implemented method for facilitating electronic data interchange (“EDI”) communication. An EDI document from a first trading partner is in a first format, with data in a plurality of fields. The fields are mapped to fields of an EDI standard. The data in the mapped fields are translated to an intermediate format to create an intermediate format file. Rules, which may be customized, may be applied to the intermediate format file. The rules may include business rules customized for the first trading partner, math rules and/or logic rules. The intermediate format file may be verified to determine whether it complies with the EDI standard and/or the business rules of the first trading partner. The data from the intermediate format to a second format compatible with a computer system of a second trading partner, to create a second format file.

Abstract: Methods, systems, and apparatuses are disclosed for a computer-implemented method for facilitating electronic data interchange (“EDI”) communication. An EDI document from a first trading partner is in a first format, with data in a plurality of fields. The fields are mapped to fields of an EDI standard. The data in the mapped fields are translated to an intermediate format to create an intermediate format file. Rules, which may be customized, may be applied to the intermediate format file. The rules may include business rules customized for the first trading partner, math rules and/or logic rules. The intermediate format file may be verified to determine whether it complies with the EDI standard and/or the business rules of the first trading partner. The data from the intermediate format to a second format compatible with a computer system of a second trading partner, to create a second format file.

Abstract: A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

Abstract: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes a second capacitor plate (160) located over the insulator (130) and a top-level dielectric layer (199) located at least partially along a sidewall of the second capacitor plate (160).

Abstract: A method for assembling a whole semiconductor wafer (101) with a plurality of device units (120) having metal contact pads. Each contact pad has a patterned barrier metal layer and a metal stud (103, preferably copper or nickel) with an outer surface suitable to form metallurgical bonds without melting. A leadframe suitable for the whole wafer is provided, which has a plurality of segments groups (102), each group suitable for one device unit; each segment has first (102a) and second ends (102b) covered by solderable metal. A predetermined amount of solder paste (104) is placed on each of the first segment ends. The leadframe is then aligned with the wafer so that each of the paste-covered segment ends is aligned with the corresponding metal stud of the respective device unit. The leadframe is connected to the wafer and the whole wafer is encapsulated (105) so that the device units and the first segment ends are covered, while the second segment ends remain exposed.

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.