Abstract: In some examples, a system can include a microcontroller to initialize a counter to a predetermined value for each image component of an image data slice. The microcontroller can also store a number of received bits for each image component in a data structure and generate a pre-allocation signal indicating that additional bits of data for one of the image components are to be requested and stored in the data structure, wherein the pre-allocation signal is to be generated in response to determining that the counter is below the predetermined value. The microcontroller can also increase the counter by the predetermined value and transmit an address from the data structure to a display device in response to detecting a valid signal.

Abstract: In some examples, a system can include a microcontroller to initialize a counter to a predetermined value for each image component of an image data slice. The microcontroller can also store a number of received bits for each image component in a data structure and generate a pre-allocation signal indicating that additional bits of data for one of the image components are to be requested and stored in the data structure, wherein the pre-allocation signal is to be generated in response to determining that the counter is below the predetermined value. The microcontroller can also increase the counter by the predetermined value and transmit an address from the data structure to a display device in response to detecting a valid signal.

Abstract: Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Abstract: Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Abstract: An embodiment of the invention includes a hardware architecture for, as an example, mobile computing devices. The architecture includes a physical layer that can be configured to be shared across one or more display panels that, in some instances, have different resolutions and bandwidth requirements. Using a shared physical layer removes one of the physical layers typically needed for multiple display devices (e.g., smart phones with two displays). In one embodiment, one physical layer includes two or more reference clock lanes so data lanes can be shared across two or more links The shared physical layer may be configured via a display driver. Other embodiments are described herein.

Abstract: Provided are a method, system, and program for managing Input/Output (I/O) requests in a cache memory system. A request is received to data at a memory address in a first memory device, wherein data in the first memory device is cached in a second memory device. A determination is made as to whether to fetch the requested data from the first memory device to cache in the second memory device in response to determining that the requested data is not in the second memory device. The requested data in the first memory device is accessed and the second memory device is bypassed to execute the request in response to determining not to fetch the requested data from the first memory device to cache in the second memory device.