Abstract: A system includes an image sensor structure and a flow cell. The image sensor structure includes an image layer disposed over a base substrate. A device stack is disposed over the image layer. A bond pad is disposed in the device stack. A passivation stack is disposed over the device stack and the bond pad. An array of nanowells is disposed in a top layer of the passivation stack. A through-silicon via (TSV) is in electrical contact with the bond pad. The TSV extends through the base substrate. A redistribution layer (RDL) is disposed on a bottom surface of the base substrate. The RDL is in electrical contact with the TSV. The flow cell is disposed upon the top layer of the passivation stack to form a flow channel therebetween. The flow channel is disposed over the array of nanowells and the bond pad.

Abstract: A MRAM device includes a magnetic tunnel junction containing a reference layer having a fixed magnetization direction, a free layer, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, a first magnetic assist layer, a second magnetic assist layer, an antiferromagnetic coupling spacer layer located between the first and second magnetic assist layers, and a first nonmagnetic spacer layer located between the free layer and the first magnetic assist layer. The antiferromagnetic coupling spacer layer is configured to provide antiferromagnetic coupling between a first magnetization direction of the first magnetic assist layer and a second magnetization direction of the second magnetic assist layer.

Abstract: The application is directed to an apparatus for allocating address space. The apparatus includes a non-transitory memory operably coupled to a processor configured to perform the step of locating a router on a network. The processor also performs the step of sending a router solicitation message including an address allocation flag to the router to reserve the address space. The processor also performs the step of receiving a router advertisement message based upon the router solicitation message including an address space option. Further, the processor performs the step of saving the address space provided in the router advertisement. The application is also directed to a computer-implemented apparatus for communicating address space between routers. The application is also directed to a computer-implemented apparatus for reallocating assigned IP address space. The application is also directed to an apparatus for registering a node with a router.

Abstract: An apparatus for transmitting packets by using a timer interrupt service routine is provided. When a task for transmitting a user datagram protocol (UDP) packet occurs while a central processing unit processes at least one task, the apparatus generates a timer interrupt event for each time set considering a packet transmission interval and calls a timer interrupt service routine, and transmits a UDP packet at equal intervals to a destination by using the timer interrupt service routine.

Abstract: Poor BSE estimation accuracy resulting from conventional Extended Kalman Filtering (EKF) approaches using RF OI sensors mounted on the ground as a remote bullet tracking sensor motivated the design and development of the present disclosure. The observer based BSE removes EKF process noise (state noise) and measurement noise (OI sensor noise) covariance matrices selection and tuning which have been long recognized by the estimation community as a time consuming process during the design stage; requires no consideration of interactions when having the control input signal as part of the state propagation equation; and provides a significant improvement in velocity estimation accuracy, in some cases to less than 1 m/s errors in all axes, thereby meeting the miss distance requirement with amble margin.

Abstract: A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

Abstract: A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

Abstract: Service Layer adaptation may be realized through one or more adaptation rules that are programmed by server administrators in a structured but flexible manner. As part of integrating the adaptive control into its operations, a Service Layer may be configured to provide the capability to receive requests in which an adaptation rule may be specified, to provide indications through response codes returned to requestors that the Service Layer is not able to process a request due to a reduced functional state, and to send a request for more server resources or move an application, a service, or a service instance to another platform.

Abstract: A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.

Abstract: The present disclosure generally relates to data storage devices, and more specifically, to a magnetic media drive employing a magnetic recording head. The head includes a trailing shield, a main pole, an STO disposed between the trailing shield and the main pole, and a non-magnetic conductive structure adjacent to the main pole and in contact with the STO. The STO includes an FGL and an SPL, and the FGL is disposed between the main pole and the SPL. The FGL includes a side extending over the main pole and at least a portion of the non-magnetic conductive structure. With the FGL disposed proximate to the main pole and over at least a portion of the non-magnetic conductive structure, current crowding and disturbance from the trailing shield are minimized.

Abstract: Mobile robotic platforms include a robotic device and a pair of laser scanners. The robotic device is positioned near a front of the mobile robotic platform while the laser scanners are positioned on the sides of the mobile robotic platform. When the mobile robotic platform is located in a selected position relative to an assembly with the front of the mobile robotic platform facing the assembly, the scanners are set to a scan field area of either a selected area for a safety zone around the sides of the mobile robotic platform or a default area within a predetermined distance from the sides. Upon detection of an intrusion into the scan field area of the laser scanners, the robotic device and/or the mobile robotic platform is stopped to prevent harm to a person whom may have inadvertently intruded into the scan field areas around the mobile robotic platform.

Abstract: Embodiments of the present disclosure relate to methods, devices, apparatuses and computer readable storage media for Uplink Control Information (UCI) design. The method comprises determining, at a terminal device, a matrix comprising a set of non-zero linear combination coefficients for quantizing a channel between the terminal device and a network device, the matrix having spatial components and frequency components; shifting the frequency components of the matrix circularly, such that a target coefficient of the set of non-zero linear combination coefficients is located in a frequency component with a predetermined index of the frequency components in a shifted matrix; generating a first indication indicating the spatial component associated with the target coefficient in the matrix; and transmitting, to the network device, uplink control information comprising the first indication. In this way, a new solution for designing the UCI may reduce the overhead for reporting the parameters in the UCI.

Abstract: Described herein are flexible implantable occluding devices that can, for example, navigate the tortuous vessels of the neurovasculature. The occluding devices can also conform to the shape of the tortuous vessels of the vasculature. In some embodiments, the occluding devices can direct blood flow within a vessel away from an aneurysm or limit blood flow to the aneurysm. Some embodiments describe methods and apparatus for adjusting, along a length of the device, the porosity of the occluding device. In some embodiments, the occluding devices allows adequate blood flow to be provided to adjacent structures such that those structures, whether they are branch vessels or oxygen-demanding tissues, are not deprived of the necessary blood flow.

Abstract: An integrated circuit (IC) comprises a regulator circuit, a bootstrap control circuit, and a gate driver that drives a transistor pair in buck or boost mode to switch current through an inductor. The IC has a VIN terminal coupled to receive a voltage generated from an AC power source, a STR terminal coupled to receive a voltage from a stored power source (e.g., a capacitor bank), and a HSB terminal that is capacitively coupled to the inductor. When bucking or boosting, the regulator circuit generates VDD supply voltage from the stored power source, supplies the VDD supply voltage onto the bootstrap control circuit, and the bootstrap control circuit generates a gate driver supply voltage that is supplied to the gate driver circuit. When not bucking or boosting, voltage on the HSB terminal is maintained between a voltage threshold from the AC power source without draining the stored power source.

Abstract: The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2VLXcontiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

Abstract: The present disclosure generally relates to data storage devices, and more specifically, to a magnetic media drive employing a magnetic recording head. The head includes a trailing shield, a main pole, side shields surrounding at least a portion of the main pole, and a structure disposed between the trailing shield and the main pole. The structure includes one or more layers and a seed layer. The seed layer is connected to one or more electrical leads to provide an electrical path from the leads to the one or more layers during operation. The seed layer guides the electrical current to the one or more layers and improves heat dissipation of the one or more layers, leading to a reduction in hot spots formed in the one or more layers.

Abstract: A method and apparatus for building an assembly fixture for holding a fuselage assembly. A number of cradle fixtures may be driven across a floor to an assembly area. The number of cradle fixtures may be configured to form the assembly fixture.