Abstract: A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Abstract: A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art.

Abstract: A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art.

Abstract: A thick plated interconnect (80) may be fabricated by forming a metal layer (20) above a semiconductor layer (12). A dielectric layer (22) may be formed on the metal layer (20). A via (24) may be formed in the dielectric layer (22) to expose the metal layer (20). A copper lead (50) may be formed electrically coupled to the metal layer (20) through the via (24) of the dielectric layer (22). A barrier member (88) may be formed on the copper lead (50). A bondable member (86) comprising aluminum may be formed on the barrier member (88).

Abstract: A thick plated interconnect (80) comprising a copper lead (50) and a bonding cap (84) coupled to the copper lead (50). The bonding cap (84) may include a bondable member (86) formed from a bondable layer (62) comprising aluminum. A barrier member (88) may be formed from a barrier layer (60). The barrier member (88) may be disposed between the bondable member (86) and the copper lead (50).

Abstract: A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

Abstract: A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

Abstract: A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.