Abstract: A device and method for increasing solid holdup in a reaction crystallizer are disclosed. The device includes a discharge pipe, a clear liquid pipe, a clear liquid tank and a gas collecting pipe. A lower end of the discharge pipe is inserted into the crystallizer below the liquid level, while that of the clear liquid pipe is inserted into the clear liquid tank below the liquid level. By using the gas collecting pipe, the reaction crystallizer and the clear liquid tank are communicated all the time. When feeding, a liquid-solid mixture in the crystallizer automatically enters the discharge pipe and flows upward slowly therein, during which solid particles gradually settle down and automatically fall back into the crystallizer while the clear liquid keeps on flowing upward, enters the clear liquid pipe and thereby flows into the clear liquid tank. The clear liquid tank maintains a constant liquid level via overflowing.

Abstract: The disclosure provides a device and method for extracting a clean liquid from a slurry reactor in an environment-friendly and energy-saving manner. The method mainly includes the following steps: S1. siphoning slurry in the slurry reactor into a material collecting pipe, and then spraying the slurry into a settling tank, so that solid particles settle in the settling tank and return to the slurry reactor through a discharging pipe; S2. making supernatant in the settling tank flow upward along a settling pipe, and then flow downward at a pipe intersection into a clear liquid pipe and flow into a clear liquid transition tank; S3. discharging liquid from the clear liquid transition tank in an overflow manner to keep the constant liquid level and a pressure required for siphoning; and S4.

Abstract: A device and method for increasing solid holdup in a reaction crystallizer are disclosed. The device includes a discharge pipe, a clear liquid pipe, a clear liquid tank and a gas collecting pipe. A lower end of the discharge pipe is inserted into the crystallizer below the liquid level, while that of the clear liquid pipe is inserted into the clear liquid tank below the liquid level. By using the gas collecting pipe, the reaction crystallizer and the clear liquid tank are communicated all the time. When feeding, a liquid-solid mixture in the crystallizer automatically enters the discharge pipe and flows upward slowly therein, during which solid particles gradually settle down and automatically fall back into the crystallizer while the clear liquid keeps on flowing upward, enters the clear liquid pipe and thereby flows into the clear liquid tank. The clear liquid tank maintains a constant liquid level via overflowing.

Abstract: A device and method for increasing solid holdup in a reaction crystallizer are disclosed. The device includes a discharge pipe, a clear liquid pipe, a clear liquid tank and a gas collecting pipe. A lower end of the discharge pipe is inserted into the crystallizer below the liquid level, while that of the clear liquid pipe is inserted into the clear liquid tank below the liquid level. By using the gas collecting pipe, the reaction crystallizer and the clear liquid tank are communicated all the time. When feeding, a liquid-solid mixture in the crystallizer automatically enters the discharge pipe and flows upward slowly therein, during which solid particles gradually settle down and automatically fall back into the crystallizer while the clear liquid keeps on flowing upward, enters the clear liquid pipe and thereby flows into the clear liquid tank. The clear liquid tank maintains a constant liquid level via overflowing.

Abstract: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.

Abstract: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.

Abstract: Embodiments of an edge detector and related methods are disclosed. One method embodiment for detecting the rising and/or falling edge of an input clock signal of unknown phase and frequency includes providing a reference clock signal of a known phase and frequency to an edge detection circuit; dividing and phase shifting the reference clock signal to provide a plurality of meta flip-flop clock signals; providing the plurality of meta flip-flop clock signals and an input clock signal to a plurality of flip-flop pairs that provide meta-stability resolution; selecting the earliest output signal of the plurality of flip-flop pairs to register a transition on the input clock signal; providing a signal corresponding to the transition to an edge detection circuit; and providing an edge detect indication at the edge detection circuit during one of the corresponding high and low phase of the input clock signal.

Abstract: Embodiments of an edge detector and related methods are disclosed. One method embodiment for detecting the rising and/or falling edge of an input clock signal of unknown phase and frequency includes providing a reference clock signal of a known phase and frequency to an edge detection circuit; dividing and phase shifting the reference clock signal to provide a plurality of meta flip-flop clock signals; providing the plurality of meta flip-flop clock signals and an input clock signal to a plurality of flip-flop pairs that provide meta-stability resolution; selecting the earliest output signal of the plurality of flip-flop pairs to register a transition on the input clock signal; providing a signal corresponding to the transition to an edge detection circuit; and providing an edge detect indication at the edge detection circuit during one of the corresponding high and low phase of the input clock signal.

Abstract: Two synchronizing flip-flops synchronize the transitions of a slow clock to a fast clock. The state of a version of the synchronized slow clock is stored by a last-state flip-flop that is clocked on an edge of the fast clock. The last-state flip-flop is compared by logic to a version of the synchronized slow clock to produce a pulse with a width determined by either a phase of the fast clock or a cycle of the fast clock.