Abstract: Trenches may be formed in the upper surfaces of a pair of wafers. Each trench may be coated with a catalyst that is capable of removing oxygen or hydrogen from a fluid used for cooling in a system making use of the electroosmotic effect for pumping. Channels may be formed to communicate fluid to and from the trench coated with the catalyst. The substrates may be combined in face-to-face abutment, for example using copper-to-copper bonding to form a re-combiner.

Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.

Abstract: An electroosmotic pump may be fabricated using semiconductor processing techniques with a nanoporous open cell dielectric frit. Such a frit may result in an electroosmotic pump with better pumping capabilities.

Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.

Abstract: An integrated electroosmotic pump may be incorporated in the same integrated circuit package with a re-combiner, and an integrated circuit chip to be cooled by fluid pumped by the electroosmotic pump.

Abstract: In one embodiment, a capacitor comprises a substrate defining a first electrical terminal; a catalyst layer disposed on the substrate; a plurality of carbon nanotubes disposed on the catalyst layer; a dielectric layer disposed over the plurality of carbon nanotubes; and a conductive layer disposed on the dielectric layer and defining a second electrical terminal.

Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.

Abstract: A microelectronic substrate including at least one microelectronic device disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic devices, or a plurality microelectronic devices encapsulated without the microelectronic substrate core. At least one conductive via extended through the substrate, which allows electrical communication between opposing sides of the substrate. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic device, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

Abstract: Expanded bond pads are formed over a passivation layer on a semiconductor wafer before the wafer is diced into individual circuit chips. After dicing, the individual chips are packaged by fixing each chip within a package core and building up one or more metallization layers on the resulting assembly. In at least one embodiment, a high melting temperature (lead free) alternative bump metallurgy (ABM) form of controlled collapse chip connect (C4) processing is used to form relatively wide conducting platforms over the bond pads on the wafer.

Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.

Abstract: The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing electro-osmotic pumps and micro-channels.

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back surface of the microelectronic die which has a metallization layer disposed thereon. A protective layer is disposed on the metallization layer prior to encapsulation, such that when the portion of the encapsulation material is removed, the protective layer prevents the metallization layer from being damaged. After the portion of the encapsulation material is removed, the protective layer is removed and the metallization layer is exposed. A heat spreader may then be attached to the microelectronic die by abutting the heat spreader against the metallization layer and reflowing the metallization layer.

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back surface of the microelectronic die which has a metallization layer disposed thereon. A protective layer is disposed on the metallization layer prior to encapsulation, such that when the portion of the encapsulation material is removed, the protective layer prevents the metallization layer from being damaged. After the portion of the encapsulation material is removed, the protective layer is removed and the metallization layer is exposed. A heat spreader may then be attached to the microelectronic die by abutting the heat spreader against the metallization layer and reflowing the metallization layer.

Abstract: A microelectronic device includes a microelectronic die having an interfacial metal layer deposited over an active surface thereof to perform a signal distribution function within the device. The microelectronic die is fixed within a package core to form a die/core assembly. One or more metallization layers may then be built up over the die/core assembly as part of a packaging scheme. The interfacial metal layer can be applied either before or after the die is fixed within the package core. In one approach, the interfacial layer is applied during wafer-level processing.

Abstract: An electroosmotic pump may be fabricated using semiconductor processing techniques with a nanoporous open cell dielectric frit. Such a frit may result in an electroosmotic pump with better pumping capabilities.

Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.

Abstract: An electroosmotic pump may be fabricated using semiconductor processing techniques with a nanoporous open cell dielectric frit. Such a frit may result in an electroosmotic pump with better pumping capabilities.

Abstract: A method for electrically coupling a first set of electrically conductive pads on a first semiconductor substrate to a second set of electrically conductive pads on a second semiconductor substrate is described. Dielectric material of a first thickness is deposited on at least one set of the first and second sets of electrically conductive pads. The first and second semiconductor substrates are then attached together such that such that the first and second sets of pads are substantially aligned parallel to one another and such that the dielectric material is disposed between the first and second sets of electrically conductive pads.

Abstract: The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing electro-osmotic pumps and micro-channels.

Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.