Patents by Inventor Que T. Tran

Que T. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9934355
    Abstract: A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: April 3, 2018
    Assignee: Tektronix, Inc.
    Inventors: Patrick A. Smith, David L. Kelly, Que T. Tran, Shane A. Hazzard
  • Patent number: 8924175
    Abstract: A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: December 30, 2014
    Assignee: Tektronix, Inc.
    Inventors: Patrick A. Smith, David L. Kelly, Que T. Tran, Shane A. Hazzard
  • Publication number: 20130231883
    Abstract: A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.
    Type: Application
    Filed: April 12, 2013
    Publication date: September 5, 2013
    Applicant: Tektronix, Inc.
    Inventors: Patrick A. Smith, David L. Kelly, Que T. Tran, Shane A. Hazzard
  • Patent number: 8386857
    Abstract: A test and measurement instrument includes a pattern detector for detecting a beginning sequence in a signal under test (SUT), and generates a synchronization signal. In response to the synchronization signal, a memory outputs a reference test pattern. A symbol comparator compares the reference test pattern with the SUT. The symbol comparator can produce a symbol error rate. One or more 8b to 10b converters receives the SUT from the input and the digitized data from the memory, and converts the data from an 8b coded format to a 10b coded format. A bit comparator compares the 10b coded reference test pattern with the 10b coded SUT in response to the symbol comparator. The bit comparator is coupled to a bit error counter, which produces a bit error rate independent of any disparity errors that may be present in the incoming digitized data received by the test and measurement instrument.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: February 26, 2013
    Assignee: Tektronix, Inc.
    Inventor: Que T. Tran
  • Patent number: 8327206
    Abstract: A blanking primitive masking circuit has a detection and handling circuit that receives data containing blanking primitives. The detection and handling circuit generates a dynamic blanking signal when blanking primitives are detected. The received data is delayed and provided to a pattern detector that generates a synchronization signal provided to a memory and a phase sync signal provided to the detection and handling circuit and to a comparator. The comparator receives reference data from the memory, the delayed data, and the dynamic blanking signal. The comparator compares the reference data with the delayed data and generates bit error outputs from mismatched reference data bits and delayed data bits when the dynamic blanking signal from the detection and handling circuit is absent and suppressing the generation bit error outputs when the blanking primitive are in the delay data and the dynamic blanking signal is present.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: December 4, 2012
    Assignee: Tektronix, Inc.
    Inventor: Que T. Tran
  • Publication number: 20110271155
    Abstract: A test and measurement instrument includes a pattern detector for detecting a beginning sequence in a signal under test (SUT), and generates a synchronization signal. In response to the synchronization signal, a memory outputs a reference test pattern. A symbol comparator compares the reference test pattern with the SUT. The symbol comparator can produce a symbol error rate. One or more 8b to 10b converters receives the SUT from the input and the digitized data from the memory, and converts the data from an 8b coded format to a 10b coded format. A bit comparator compares the 10b coded reference test pattern with the 10b coded SUT in response to the symbol comparator. The bit comparator is coupled to a bit error counter, which produces a bit error rate independent of any disparity errors that may be present in the incoming digitized data received by the test and measurement instrument.
    Type: Application
    Filed: April 11, 2011
    Publication date: November 3, 2011
    Applicant: TEKTRONIX, INC.
    Inventor: Que T. TRAN
  • Publication number: 20110154171
    Abstract: A blanking primitive masking circuit has a detection and handling circuit that receives data containing blanking primitives. The detection and handling circuit generates a dynamic blanking signal when blanking primitives are detected. The received data is delayed and provided to a pattern detector that generates a synchronization signal provided to a memory and a phase sync signal provided to the detection and handling circuit and to a comparator. The comparator receives reference data from the memory, the delayed data, and the dynamic blanking signal. The comparator compares the reference data with the delayed data and generates bit error outputs from mismatched reference data bits and delayed data bits when the dynamic blanking signal from the detection and handling circuit is absent and suppressing the generation bit error outputs when the blanking primitive are in the delay data and the dynamic blanking signal is present.
    Type: Application
    Filed: April 30, 2010
    Publication date: June 23, 2011
    Applicant: TEKTRONIX, INC.
    Inventor: Que T. TRAN
  • Publication number: 20100114516
    Abstract: A measurement system including a plurality of test and measurement instruments; and a hub coupled to each of the test and measurement instruments. Each of the test and measurement instruments is configured to trigger an acquisition in response to a hub event received from the hub. Acquisitions can be triggered from one, some, any, or all of the test and measurement instruments.
    Type: Application
    Filed: June 26, 2009
    Publication date: May 6, 2010
    Applicant: TEKTRONIX, INC.
    Inventors: Zhongsheng WANG, Que T. TRAN, Nicolas SCHMIDT