Abstract: An integrated circuit/printed circuit board (IC-PCB) assembly comprises a PCB and a heatsink plate. The PCB has a first side including a first patterned conductive layer with one or more thermal pads onto which one or more heat slugs of one or more ICs mount, and a second, opposing side including a second patterned conductive layer with a heatsink plate receiving pad onto which the heatsink plate mounts. The heatsink plate has one or more posts that project from a mounting surface of the heatsink plate, and when the heatsink plate is mounted to the heatsink plate receiving pad, each post extends from the second side of the PCB, through a matching hole in the PCB, and to an associated thermal pad located on the first side of the PCB.

Abstract: An integrated circuit printed circuit board (IC-PCB) assembly comprises a PCB and a heatsink plate. The PCB has a first side including a first patterned conductive layer with one or more thermal pads onto which one or more heat slugs of one or more ICs mount, and a second, opposing side including a second patterned conductive layer with a heatsink plate receiving pad onto which the heatsink plate mounts. The heatsink plate has one or more posts that project from a mounting surface of the heatsink plate, and when the heatsink plate is mounted to the heatsink plate receiving pad, each post extends from the second side of the PCB, through a matching hole in the PCB, and to an associated thermal pad located on the first side of the PCB.

Abstract: An integrated circuit/printed circuit board (IC-PCB) assembly comprises a PCB and a heatsink plate. The PCB has a first side including a first patterned conductive layer with one or more thermal pads onto which one or more heat slugs of one or more ICs mount, and a second, opposing side including a second patterned conductive layer with a heatsink plate receiving pad onto which the heatsink plate mounts. The heatsink plate has one or more posts that project from a mounting surface of the heatsink plate, and when the heatsink plate is mounted to the heatsink plate receiving pad, each post extends from the second side of the PCB, through a matching hole in the PCB, and to an associated thermal pad located on the first side of the PCB.

Abstract: An integrated circuit/printed circuit board (IC-PCB) assembly comprises a PCB and a heatsink plate. The PCB has a first side including a first patterned conductive layer with one or more thermal pads onto which one or more heat slugs of one or more ICs mount, and a second, opposing side including a second patterned conductive layer with a heatsink plate receiving pad onto which the heatsink plate mounts. The heatsink plate has one or more posts that project from a mounting surface of the heatsink plate, and when the heatsink plate is mounted to the heatsink plate receiving pad, each post extends from the second side of the PCB, through a matching hole in the PCB, and to an associated thermal pad located on the first side of the PCB.

Abstract: A wideband polar modulation transmitter includes a power amplifier (PA), a PA driver, a dynamic power supply (DPS), a PA driver VH controller, and a phase modulator. The phase modulator modulates a radio frequency (RF) carrier by an input phase modulating signal PM(t) to produce a phase modulated RF carrier. Meanwhile, the DPS produces a DPS voltage for the PA that follows an input amplitude modulating signal AM(t). Using the phase modulated RF carrier, the PA driver generates a PA drive signal VDRV for driving the PA. The PA drive signal VDRV has a high drive level VH and a low drive level VL. The PA driver VH controller is configured to control the magnitude of the high drive level VH so that it remains sufficiently high to force the PA to operate in a compressed mode (C-mode) most of the time but lowers the high drive level VH to force the PA to operate in a product mode (P-mode) during times low-magnitude events occur in the DPS voltage.

Abstract: A multi-stage radio frequency power amplifier (RFPA) includes an output stage SMPA and a driver stage SMPA. As the multi-stage RFPA operates, the magnitude of an RF switch drive signal generated by the driver stage SMPA is dynamically minimized based on I-V characteristic curves of the output stage SMPA's power transistor and the output stage SMPA's dynamically changing load line. By constraining the magnitude of the RF switch drive signal as the multi-stage RFPA operates, VGS feedthrough of the RF switch drive signal is minimized, to the extent possible. Amplitude distortion and phase distortion in the RF output that might occur due to unconstrained VGS feedthrough, particularly at low output RF power levels, are therefore avoided. Operating all stages of the multi-stage RFPA in switch mode also results in high energy efficiency and an output RF spectrum with very low wideband noise (WBN).

Abstract: Methods for mounting and dismounting thin and/or bowed semiconductor-on-diamond wafers to a carrier are disclosed that flatten said wafers and provide mechanical support to enable efficient semiconductor device processing on said semiconductor-on-diamond wafers.

Abstract: A multi-stage radio frequency power amplifier (RFPA) includes an output stage SMPA and a driver stage SMPA. As the multi-stage RFPA operates, the magnitude of an RF switch drive signal generated by the driver stage SMPA is dynamically minimized based on I-V characteristic curves of the output stage SMPA's power transistor and the output stage SMPA's dynamically changing load line. By constraining the magnitude of the RF switch drive signal as the multi-stage RFPA operates, VGS feedthrough of the RF switch drive signal is minimized, to the extent possible. Amplitude distortion and phase distortion in the RF output that might occur due to unconstrained VGS feedthrough, particularly at low output RF power levels, are therefore avoided. Operating all stages of the multi-stage RFPA in switch mode also results in high energy efficiency and an output RF spectrum with very low wideband noise (WBN).

Abstract: Methods for mounting and dismounting thin and/or bowed semiconductor-on-diamond wafers to a carrier are disclosed that flatten said wafers and provide mechanical support to enable efficient semiconductor device processing on said semiconductor-on-diamond wafers.

Abstract: Methods for mounting and dismounting thin and/or bowed semiconductor-on-diamond wafers (401) to a carrier (407) are disclosed that flatten said wafers and provide mechanical support to enable efficient semiconductor device processing on said semiconductor-on-diamond wafers.

Abstract: A high-power, high-frequency radio frequency power amplifier includes an output stage and a single-phase driver. The output stage is arranged in a Class-D amplifier configuration and includes a first depletion mode field effect transistor (FET), a second depletion mode FET, and a bootstrap path that couples the output of the output stage to the gate of the second FET. The first and second depletion mode FETs are switched out-of-phase and between fully-ON and fully-OFF states, under the direction of the single-phase driver. The single-phase driver directly controls the ON/OFF state of the first depletion mode FET and provides a discharge path through which the input gate capacitor of the second depletion mode FET in the output stage can discharge to turn OFF the second depletion mode FET. The bootstrap path provides a current path through which the input gate capacitor of the second depletion mode FET can charge to turn the second depletion mode FET ON.

Abstract: A high-power, high-frequency radio frequency power amplifier includes an output stage and a single-phase driver. The output stage is arranged in a Class-D amplifier configuration and includes a first depletion mode field effect transistor (FET), a second depletion mode FET, and a bootstrap path that couples the output of the output stage to the gate of the second FET. The first and second depletion mode FETs are switched out-of-phase and between fully-ON and fully-OFF states, under the direction of the single-phase driver. The single-phase driver directly controls the ON/OFF state of the first depletion mode FET and provides a discharge path through which the input gate capacitor of the second depletion mode FET in the output stage can discharge to turn OFF the second depletion mode FET. The bootstrap path provides a current path through which the input gate capacitor of the second depletion mode FET can charge to turn the second depletion mode FET ON.

Abstract: A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer.

Abstract: A method for integrating wide-gap semiconductors, and specifically, gallium nitride epilayers, with synthetic diamond substrates is disclosed. Diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited or formed on a layered structure that comprises at least one layer of gallium nitride. Methods for manufacturing GaN-on-diamond wafers with low bow and high crystalline quality are disclosed along with preferred choices for manufacturing GaN-on-diamond wafers and chips tailored to specific applications.

Abstract: A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer.

Abstract: A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer.

Abstract: Methods for manufacturing semiconductor wafer structures are described which exhibit improved lifetime and reliability. The methods comprise transferring an active semiconductor layer structure from a native non-lattice-matched semiconductor growth substrate to a working substrate, wherein strain-matching layers, and optionally a portion of the active semiconductor layer structure, are removed. In certain embodiment, the process of attaching the active semiconductor layer structure to the working substrate includes annealing at an elevated temperature for a specified time.

Abstract: A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.

Abstract: Methods for mounting and dismounting thin and/or bowed semiconductor-on-diamond wafers (401) to a carrier (407) are disclosed that flatten said wafers and provide mechanical support to enable efficient semiconductor device processing on said semiconductor-on-diamond wafers.

Abstract: A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.