Abstract: A method and system for mapping the flow data that will be the subject of wavelet transform equations to a system comprising adders, subtractors, multipliers and/or dividers to perform the mathematical functions set forth in the particular wavelet transform. A shift register is utilized to continually flow the individual data bytes of the data file being processed through the system. By mapping these hardware components to perform the computations involved in wavelet transform equations, an entire data file (e.g., a digital image) can be processed serially as it flows through the shift register triggered by a clock pulse to the shift register.

Abstract: The present invention is a method and system for mapping the flow data that will be the subject of wavelet transform equations to a system comprising adders, subtractors, multipliers and/or dividers to perform the mathematical functions set forth in the particular wavelet transform. A shift register is utilized to continually flow the individual data bytes of the data file being processed through the system. By mapping these hardware components to perform the computations involved in wavelet transform equations, an entire data file (e.g., a digital image) can be processed serially as it flows through the shift register triggered by a clock pulse to the shift register. This eliminates the need for process computers and storage for conducting the multiple read-process-write steps required of prior art wavelet transform processors.

Abstract: An apparatus and method is disclosed for generating a bit reversed sequence. The apparatus includes a reverse addition means for adding binary words in most significant to least significant bit order with the overflow or carry bit propagated to the left. The invention is used to generate a bit reversed address and/or an address sequence that is mapped into a "closed" space.

Abstract: A method for performing computations with an asynchronous linear array of multiple processing stages is disclsoed. The linear array comprises multiple processing stages interspersed with flow control flag mechanisms and with dual port linking memories. The method utilizes the flow control flag mechanisms between processing stages to control the flow of computations through the array.

Abstract: A Memory-Linked Wavefront Array Processor (MWAP) is disclosed which computes a broad range of signal processing, scientific and engineering problems at ultra-high speed. The memory-linked wavefront array processor is an array of identical programmable processing elements linked together by dual-port memory elements that contain a set of special purpose control flags. All communication in the network is done asynchronously via the linking memory elements, thus providing asynchronous global communication with the processing array. The architecture allows coefficients, intermediate calculations and data used in computations to be stored in the linking elements between processing stages. The novel architecture also allows coefficients, intermediate calculations and data to be passed between the processing elements in any desired order not restricted by the order data is to be used by the receiving processing element.