Abstract: A data processing network includes multiple processing devices, multiple memory cards of main storage, and a shared interface. Each of the memory cards includes memory arrays, an internal register for temporarily storing a pointer data word read from the arrays, and logic circuitry. When one of the processing devices sends a tag bit extraction or tag bit insertion command to one of the memory cards, the pointer to be modified is retrieved from a selected address in the memory arrays and latched into the internal register. The logic circuitry provides the tag bits to an AND logic gate and provides the AND gate output to the processor in the case of tag bit extraction. For tag bit insertion, the circuitry applies the pointer from the arrays and a tag bit input from the processor, as inputs to a multiplexer and provides the multiplexer output back to the selected address in the arrays.

Abstract: A data processing network includes multiple processing devices, multiple memory cards of main storage, and a main storage interface shared by the processors and memory cards. Each of the memory cards includes memory arrays, a hold register for retaining a data pattern stored to the arrays, a compare register and logic circuity. For a memory array diagnostic test, one of the processing devices sends a compare command (including address information) and the data pattern to one of the memory cards. In response, the logic circuity on the selected memory card stores the data pattern to its hold register and writes the data pattern into its memory arrays, then reads the data out of the memory arrays into its compare register. The contents of the compare and hold registers are compared, and an error indication provided to the processing device in the event that these registers' contents are not the same.

Abstract: A data processing network includes multiple processing devices, multiple memory cards of main storage, and a shared interface. Each of the memory cards includes memory arrays, an internal register for temporarily storing a data word read from the arrays, and logic circuitry. When one of the processing devices sends a set or reset command to one of the memory cards, the processor also sends a data mask. A data word to be modified is retrieved from a selected location in the memory arrays and latched into the internal register. The logic circuitry applies the data mask to a data word in the internal register, to modify the data word according to the data mask, then returns the data word to the selected location in the arrays.

Abstract: A system for altering physical addresses of semiconductor memory cards to locate an error-free portion to provide a contiguous range of storage which is free from errors. The system contains a memory card ID register which stores the physical addresses of memory cards in positions corresponding to logical addresses. The system evaluates the results of routine tests of memory and rearranges the physical addresses stored in the memory card ID register to provide an error-free portion at the desired logical address range. A separate memory configuration register stores a value representing the size of the memory cards. The value stored in the memory configuration register selects a subset of the logical memory address bits to obtain a logical card address. The logical card address selects a position in the memory card ID register to obtain the physical address of the memory card.

Abstract: A real time data transformation and transmission apparatus transforms data from a first data device and transfers the transformed data to a second data device which need not have a data transfer rate consistent with the first data device. Data from the first data device is divided into blocks and is compressed by a compression device and written into a buffer. A controller controls the buffer to transmit compressed data to the second data device as a function of the data receiving rate of the second data medium provided that the buffer contains a predetermined amount of data. While the buffer is transmitting data, the compressor is compressing further blocks of data which are being written to the buffer such that the predetermined amount of data is stored in the buffer upon completion of the buffer transmitting a block of data. This ensures that complete blocks of data are transmitted to the second data medium at the data receiving rate of the second data medium.