Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for an on-die capacitor. A memory chip comprises an array of memory cells. A capacitor is electrically coupled to an array of memory cells. A capacitor receives at least a portion of discharged electricity from an operation for an array of memory cells. A capacitor supplies electricity back to an array of memory cells during a subsequent operation for an array of memory cells.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for reducing routing signals. An apparatus includes a first block decoder circuit that senses bad block data of a first latch circuit corresponding to a first memory block and couple the bad block data onto a bus. An apparatus includes a comparator circuit that compares the bad block data against a reference, sets a bad block flag, and routes the bad block flag on a routing line across an array of storage elements. An apparatus includes a second block decoder circuit that receives the bad block flag from the routing line, determines a condition of the first memory block based on the bad block flag, and determines a generation of a block selection signal for selecting a second memory block.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for an on-die capacitor. A memory chip comprises an array of memory cells. A capacitor is electrically coupled to an array of memory cells. A capacitor receives at least a portion of discharged electricity from an operation for an array of memory cells. A capacitor supplies electricity back to an array of memory cells during a subsequent operation for an array of memory cells.

Abstract: This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for reduced routing signals. An apparatus includes a generator circuit that generates switch gate voltages for two or more word line switches. Two or more word line switches are on opposite sides of an array of memory elements and are for coupling word line voltages to word lines. An apparatus includes a word line switch circuit that supplies switch gate voltages to two or more word line switches. An apparatus includes a transistor control circuit that supplies select gate voltages to two or more select gates. Two or more select gates control select gate drain transistors. Select gate voltages are different from switch gate voltages. Select gate voltages and switch gate voltages are both based on a routing line voltage on a routing line that extends across an array of memory elements.

Abstract: This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.

Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

Abstract: A powder coating composition is provided herein. The powder coating composition includes a glycidyl-functionalized (meth)acrylic resin as a film-forming binder, a cross-linking agent (hardener) for the binder, particles chosen from the group comprising aluminum oxide Al2O3 and aluminum hydroxide Al(OH)3 particles, and a coating additive, the wt % based on the total weight of the powder coating composition. A process for the production of a scratch resistant powder coating is also provided herein. The process includes the steps of a) applying a transparent clear coat or a pigmented top coat directly onto a substrate surface or onto a prior coating, and b) curing the clear coat or the top coat applied in step a) wherein the transparent clear coat or the pigmented top coat includes the powder coating composition.

Abstract: Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.

Abstract: Apparatuses, systems, and methods are disclosed for accessing non-volatile memory. A bit line is coupled to storage cells for a non-volatile memory element. A sense amplifier is coupled to a bit line. A sense amplifier includes a sense circuit and a bias circuit. A sense circuit senses an electrical property of a bit line for reading data from one or more storage cells, and a bias circuit applies a bias voltage to the bit line for writing data to one or more storage cells. A bias circuit and a sense circuit comprise separate parallel electrical paths within a sense amplifier.

Abstract: The invention relates to copper-containing metal pigments, wherein the copper-containing metal pigments have an elemental copper content of at least 50 wt.-%, relative to the total weight of the uncoated copper-containing metal pigment, wherein the copper-containing metal pigments have at least one enveloping metal oxide layer and at least one enveloping chemically non-reactive plastic layer, wherein the sum of the amounts of the at least one chemically non-reactive plastic layer and of the at least one metal oxide layer lies in a range of from 10 to 50 wt.-%, relative to the weight of the uncoated metal pigment, and the weight ratio of the at least one metal oxide layer to the at least one chemically non-reactive plastic layer lies in a range of from 1:2 to 1:20. The invention furthermore relates to a method for producing these pigments and the use thereof.

Abstract: Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.

Abstract: A method for determining whether a used electronic device has theft-detection software turned on. Such a method may be used at a repurchase facility or an automated kiosk to reject devices that may be stolen.

Abstract: The present invention provides a powder coating composition comprising A) 30 to 90 wt % of at least one glycidyl-functionalised (meth)acrylic resin as film-forming binder, B) 30 to 90 wt % of at least one cross-linking agent (hardener) for the binder, C) 0.01 to 20 wt % of particles selected from the group consisting of aluminium oxide Al2O3 and aluminium hydroxide Al(OH)3 particles having an average particles size in the range of 0.1 to 10 ?m, and D) 0.05 to 50 wt % of at least one coating additive, and optionally, pigment and/or filler, the wt % based on the total weight of the powder coating composition, providing coatings with improved smoothness and high scratch resistance, and surprisingly, gloss and transparency of clear coatings with high quality.

Abstract: The invention relates to a method for coating metallic effect pigments with silicon oxide, in which alkoxysilane(s) and/or silicon halide(s) in organic solvent are reacted with water in the presence of metallic effect pigments, where the reaction includes at least two steps, where (a) the reaction is carried out with addition of acid in a first step and with addition of base in a second step or where (b) the reaction is carried out with addition of base in a first step and with addition of acid in a second step. The invention further relates to the coated metallic effect pigments producible by way of the method of the invention, and also to the use thereof.

Abstract: The invention relates to copper-containing metal pigments, wherein the copper-containing metal pigments have an elemental copper content of at least 50 wt. %, relative to the total weight of the uncoated copper-containing metal pigment, wherein the copper-containing metal pigments have at least one enveloping metal oxide layer and at least one enveloping chemically non-reactive plastic layer, wherein the sum of the amounts of the at least one chemically non-reactive plastic layer and of the at least one metal oxide layer lies in a range of from 10 to 50 wt. %, relative to the weight of the uncoated metal pigment, and the weight ratio of the at least one metal oxide layer to the at least one chemically non-reactive plastic layer lies in a range of from 1:2 to 1:20. The invention furthermore relates to a method for producing these pigments and the use thereof.

Abstract: The invention relates to a metallic effect pigment selected from platelet-shaped aluminum, platelet-shaped metallic pigments having a copper fraction of 60% to 100% by weight, and mixtures thereof, having a coating of silicon oxide SiOx, where x is a number from 1 to 2, where the coated metallic effect pigment comprises metal cations and phosphorus- and/or sulfur-containing anions present independently of one another on the metallic effect pigment surface and/or in the silicon oxide layer SiOx, and the element ratio in atomic fractions of metal cation MC and phosphorus P and/or sulfur S to silicon Si is defined by formulae (I) and (II): 100%×(MC+P)/Si??(I) and/or 100%×(MC+S)/Si??(II) and being in total in a range from 0.5% to 35%. The invention further relates to the coated metallic effect pigments producible via the method of the invention, and to the use thereof.

Abstract: The invention relates to a method for coating metallic effect pigments with silicon oxide, in which alkoxysilane(s) and/or silicon halide(s) in organic solvent are reacted with water in the presence of metallic effect pigments, where the reaction includes at least two steps, where (a) the reaction is carried out with addition of acid in a first step and with addition of base in a second step or where (b) the reaction is carried out with addition of base in a first step and with addition of acid in a second step. The invention further relates to the coated metallic effect pigments producible by way of the method of the invention, and also to the use thereof.