Patents by Inventor Qui-Ting Chen

Qui-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Termination circuits capable of receiving data signals in different formats for performing impedance matching
    Patent number: 8912819
    Abstract: A termination circuit is provided. The termination circuit includes a first receiving terminal, a second receiving terminal, a first resistive device, a second resistive device, a third resistive device, a fourth resistive device and a first switch. The first receiving terminal receives a first data signal. The second receiving terminal receives a second data signal. The first resistive device is coupled between a supply voltage and the first receiving terminal. The second resistive device is coupled between the supply voltage and the second receiving terminal. The third resistive device is coupled between the first receiving terminal and a first node. The fourth resistive device is coupled between the second receiving terminal and the first node. The first switch is coupled between the supply voltage and the first node.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 16, 2014
    Assignee: MediaTek Inc.
    Inventors: Qui-Ting Chen, Huai-Te Wang
  • Low power memory controllers
    Patent number: 8848462
    Abstract: A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 30, 2014
    Assignee: Mediatek Inc.
    Inventors: Yan-Bin Luo, Chih-Chien Hung, Qui-Ting Chen, Shang-Ping Chen
  • TERMINATION CIRCUITS CAPABLE OF RECEIVING DATA SIGNALS IN DIFFERENT FORMATS FOR PERFORMING IMPEDANCE MATCHING
    Publication number: 20140266298
    Abstract: A termination circuit is provided. The termination circuit includes a first receiving terminal, a second receiving terminal, a first resistive device, a second resistive device, a third resistive device, a fourth resistive device and a first switch. The first receiving terminal receives a first data signal. The second receiving terminal receives a second data signal. The first resistive device is coupled between a supply voltage and the first receiving terminal. The second resistive device is coupled between the supply voltage and the second receiving terminal. The third resistive device is coupled between the first receiving terminal and a first node. The fourth resistive device is coupled between the second receiving terminal and the first node. The first switch is coupled between the supply voltage and the first node.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 18, 2014
    Applicant: MEDIATEK INC.
    Inventors: Qui-Ting CHEN, Huai-Te WANG
  • LOW POWER MEMORY CONTROLLERS
    Publication number: 20130088929
    Abstract: A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.
    Type: Application
    Filed: September 14, 2012
    Publication date: April 11, 2013
    Applicant: MEDIATEK INC.
    Inventors: Yan-Bin LUO, Chih-Chien HUNG, Qui-Ting CHEN, Shang-Ping CHEN
  • Tunable equalizer and methods for adjusting the tunable equalizer
    Patent number: 8363710
    Abstract: A tunable equalizer with a tunable equalizer frequency response is provided. The tunable equalizer includes an amplifier circuit for amplifying input signals and a tunable circuit coupled to the amplifier circuit. The tunable circuit is arranged to provide a zero point in the equalizer frequency response and the zero point is adjusted according to a controllable value. When the controllable value varies according to a uniform offset, the corresponding zero point varies according to a non-uniform offset.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: January 29, 2013
    Assignee: Mediatek Inc.
    Inventors: Yan-Bin Luo, Qui-Ting Chen
  • TUNABLE EQUALIZER AND METHODS FOR ADJUSTING THE TUNABLE EQUALIZER
    Publication number: 20100111156
    Abstract: A tunable equalizer with a tunable equalizer frequency response is provided. The tunable equalizer includes an amplifier circuit for amplifying input signals and a tunable circuit coupled to the amplifier circuit. The tunable circuit is arranged to provide a zero point in the equalizer frequency response and the zero point is adjusted according to a controllable value. When the controllable value varies according to a uniform offset, the corresponding zero point varies according to a non-uniform offset.
    Type: Application
    Filed: April 21, 2009
    Publication date: May 6, 2010
    Applicant: MEDIATEK INC.
    Inventors: Yan-Bin Luo, Qui-Ting Chen