Patents by Inventor Quinghua Hubert Yue

Quinghua Hubert Yue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8378864
    Abstract: Successive approximation Analog-to-digital converters (ADCs) and related methods are disclosed. A successive approximation ADC includes a comparator with a comparator output and inputs coupled to a common model signal and a compare input. Control logic generates one or more control signals responsive to the comparator output. A capacitor array includes first sides of capacitors operably coupled to an array output. The capacitor arrays selectively couples each of second sides of the capacitors to an analog input signal and one or more input reference signals responsive to the one or more control signals. A voltage limiter is operably coupled between the array output and the compare input of the comparator and limits a voltage on the compare input to within a predefined range relative to the array output. The successive approximation ADC may also be configured differentially with a second comparator and a second voltage limiter.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: February 19, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Lijie Zhao, Song Gao, Quinghua Hubert Yue, Jeffrey G. Barrow
  • Publication number: 20120235846
    Abstract: Successive approximation Analog-to-digital converters (ADCs) and related methods are disclosed. A successive approximation ADC includes a comparator with a comparator output and inputs coupled to a common model signal and a compare input. Control logic generates one or more control signals responsive to the comparator output. A capacitor array includes first sides of capacitors operably coupled to an array output. The capacitor arrays selectively couples each of second sides of the capacitors to an analog input signal and one or more input reference signals responsive to the one or more control signals. A voltage limiter is operably coupled between the array output and the compare input of the comparator and limits a voltage on the compare input to within a predefined range relative to the array output. The successive approximation ADC may also be configured differentially with a second comparator and a second voltage limiter.
    Type: Application
    Filed: March 16, 2011
    Publication date: September 20, 2012
    Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Lijie Zhao, Song Gao, Quinghua Hubert Yue, Jeffrey G. Barrow