Patents by Inventor Quinn A. Jacobson

Quinn A. Jacobson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040162967
    Abstract: One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.
    Type: Application
    Filed: August 8, 2003
    Publication date: August 19, 2004
    Inventors: Marc Tremblay, Shailender Chaudhry, Quinn A. Jacobson
  • Publication number: 20040162968
    Abstract: One embodiment of the present invention provides a system that supports executing a fail instruction, which terminates transactional execution of a block of instructions. During operation, the system facilitates transactional execution of a block of instructions within a program, wherein changes made during the transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes. If a fail instruction is encountered during this transactional execution, the system terminates the transactional execution without committing results of the transactional execution to the architectural state of the processor.
    Type: Application
    Filed: August 8, 2003
    Publication date: August 19, 2004
    Inventors: Marc Tremblay, Shailender Chaudhry, Quinn A. Jacobson
  • Publication number: 20040163082
    Abstract: One embodiment of the present invention provides a system that facilitates executing a commit instruction, which marks the end of a block of instructions to be executed transactionally. Upon encountering the commit instruction during execution of a program, the system successfully completes transactional execution of the block of instructions preceding the commit instruction. Changes made during the transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.
    Type: Application
    Filed: August 8, 2003
    Publication date: August 19, 2004
    Inventors: Marc Tremblay, Shailender Chaudhry, Quinn A. Jacobson
  • Publication number: 20040162951
    Abstract: One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.
    Type: Application
    Filed: December 15, 2003
    Publication date: August 19, 2004
    Inventors: Quinn A. Jacobson, Marc Tremblay, Shailender Chaudhry
  • Publication number: 20040162948
    Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.
    Type: Application
    Filed: May 16, 2003
    Publication date: August 19, 2004
    Inventors: Marc Tremblay, Shailender Chaudhry, Quinn A. Jacobson
  • Publication number: 20040143821
    Abstract: Data speculations are converted to control speculations in a computer program. The conversion is applied at selected locations in the computer program to eliminate the need for hardware to perform data speculation. Since data speculation is converted to control speculation, any processor that supports out-of-order execution can be used to execute the modified computer program.
    Type: Application
    Filed: January 21, 2003
    Publication date: July 22, 2004
    Applicant: Sun Microsystems, Inc.
    Inventor: Quinn A. Jacobson
  • Patent number: 6757807
    Abstract: A processor comprising a new architectural feature called a Register Domain, where a Register Domain has a register file, at least one execution unit, and coupling circuitry between the two. A processor will typically have a plurality of Register Domains, and Register Domains may have different types of execution units within them. Individual Register Domains will be visible to a user.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: June 29, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Quinn A. Jacobson, Chiao-Mei Chuang
  • Publication number: 20040078728
    Abstract: One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation, the system receives a temporary result during execution of an in-flight instruction. Next, the system generates a parity bit for the temporary result, and stores the temporary result and the parity bit in a temporary register within the CPU. Before the temporary result is committed to the architectural state of the CPU, the system checks the temporary result and the parity bit to detect a bit error. If a bit error is detected, the system performs a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result. Otherwise, if a bit error is not detected, the system commits the temporary result to the architectural state of the CPU.
    Type: Application
    Filed: May 14, 2002
    Publication date: April 22, 2004
    Inventors: Marc Tremblay, Shailender Chaudhry, Quinn A. Jacobson
  • Publication number: 20030217325
    Abstract: One embodiment of the present invention provides a system that facilitates error correction within a register file in a central processing unit (CPU). During execution of an instruction by the CPU, the system retrieves a dataword and an associated syndrome from a source register in the register file. Next, the system uses information in the dataword and the associated syndrome to detect, and if necessary correct, an error in the dataword or associated syndrome. Note that this error detection and correction takes place in parallel with using the dataword to perform a computational operation specified by the instruction. If an error is detected, the system prevents the instruction from performing a writeback to a destination register in the register file. The system also writes a corrected dataword to the source register in the register file. Next, the system flushes the instruction pipeline, and restarts execution of the instruction so that the corrected dataword is retrieved for the computational operation.
    Type: Application
    Filed: May 14, 2002
    Publication date: November 20, 2003
    Inventors: Marc Tremblay, Shailender Chaudhry, Quinn A. Jacobson
  • Patent number: 6247121
    Abstract: In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction. The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: June 12, 2001
    Assignee: Intel Corporation
    Inventors: Haitham Akkary, Quinn A. Jacobson