Abstract: Aspects of the present invention provide an approach for integrated testing of gateway appliance software services. In an embodiment, a test request is received at a unit test framework installed on the gateway appliance. The unit test framework dynamically generates a set of stub code for processing the test request. This set of stub code executes target code (e.g., code that is being tested) of the software services. Results of the execution are verified to determine whether the code passes the test.

Abstract: Aspects of the present invention provide an approach for integrated testing of gateway appliance software services. In an embodiment, a test request is received at a unit test framework installed on the gateway appliance. The unit test framework dynamically generates a set of stub code for processing the test request. This set of stub code executes target code (e.g., code that is being tested) of the software services. Results of the execution are verified to determine whether the code passes the test.

Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: The present disclosure relates to cryoprotection of plants. The compositions and methods disclosed herein provide a means for protecting plants from frost or freeze damage or death due to sudden exposure to low temperature conditions. The present disclosure further relates to methods for providing cryoprotection to plants.

Abstract: An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: The present disclosure relates to cryoprotection of plants. The compositions and methods disclosed herein provide a means for protecting plants from frost or freeze damage or death due to sudden exposure to low temperature conditions. The present disclosure further relates to methods for providing cryoprotection to plants.

Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For minimum-phase channels, the equalization is performed in a time-forward manner. For maximum-phase channels, the equalization is performed in a time-reversed manner. More specifically, for maximum-phase channels, the filter coefficients are computed based on the channel estimates reversed in time, and the filtering and equalization operations are performed with the received block of symbols in a time-reversed order. In the context of this invention, the term “minimum-phase channel” implies that the energy of the leading part of the channel profile is greater than the energy of the trailing part. The term “maximum-phase channel” implies that the energy of the leading part of the channel profile is less than the energy of the trailing part.

Abstract: An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For minimum-phase channels, the equalization is performed in a time-forward manner. For maximum-phase channels, the equalization is performed in a time-reversed manner. More specifically, for maximum-phase channels, the filter coefficients are computed based on the channel estimates reversed in time, and the filtering and equalization operations are performed with the received block of symbols in a time-reversed order. In the context of this invention, the term “minimum-phase channel” implies that the energy of the leading part of the channel profile is greater than the energy of the trailing part. The term “maximum-phase channel” implies that the energy of the leading part of the channel profile is less than the energy of the trailing part.

Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For minimum-phase channels, the equalization is performed in a time-forward manner. For maximum-phase channels, the equalization is performed in a time-reversed manner. More specifically, for maximum-phase channels, the filter coefficients are computed based on the channel estimates reversed in time, and the filtering and equalization operations are performed with the received block of symbols in a time-reversed order. In the context of this invention, the term “minimum-phase channel” implies that the energy of the leading part of the channel profile is greater than the energy of the trailing part. The term “maximum-phase channel” implies that the energy of the leading part of the channel profile is less than the energy of the trailing part.

Abstract: A transmitter for wireless communications provides multiple types of orthogonality to improve transmit diversity. Transmit diversity is improved by using both coding and carrier frequency orthogonality. Data to be transmitted is broken into four parallel channels. Two of the channels are transmitted on a first carrier signal and the other two channels are transmitted on a second carrier signal. Channels transmitted on the same carrier signal are provided with orthogonal codes so that they may be separated by a receiver. Channels transmitted on different carrier signals may be encoded with identical orthogonal codes. The modulated carrier signals are then transmitted using at least two antennas, where one antenna is used for each carrier.

Abstract: A long code generator is disclosed that maintains a common long code state between a system with multiple spreading rates, such as a spreading rate equal to the chip rate (1×) and a spreading rate at a multiple of the chip rate (n×), such as three-times the chip rate (3×). An n× long code generator generates n bits for every clock pulse, where the clock operates at the system chip rate. n bits are generated for every clock period by having the long code mask value assume n values for each clock period. Thus, the long code mask value is changed at n times the chip rate, while the shift register is operated at the chip rate. Each of the long codes corresponding to the n long code mask values are multiplexed, for example, using an interlacing technique. The long code generator includes a conventional shift register, AND gate array, modulo-2 adder and clock.

Abstract: The invention is a method for controlling power on multiple forward link communication channels by using multiple power control sub-channels, wherein each power control sub-channel is associated with a forward link communication channel to be power controlled. A fundamental power control sub-channel and a supplemental power control sub-channel are time multiplexed onto a reverse pilot channel. Transmitted over the fundamental power control sub-channel is a fundamental power control bit for indicating to a base station to increase or decrease its transmission power over a corresponding forward fundamental channel. Transmitted over the supplemental power control sub-channel is a supplemental power control bit for indicating to a base station to increase or decrease its transmission power over a corresponding forward supplemental channel. The pilot sub-channels are preferably separated by the fundamental and supplemental power control sub-channels for time diversity purposes.

Abstract: A method of controlling the power in a wireless communication system. In one embodiment of the invention, a base station determines the information rate of a signal to be transmitted to a mobile station, and obtains the variable power control scaling factor based on this information rate. The base station then transmits the variable power control scaling factor to the mobile station. The mobile station determines a target signal quality measurement for a received signal from the base station, such as a target Eb/N0, and scales the target Eb/N0 by the variable power control scaling factor. The mobile station also obtains an information rate scaling factor based on the information rate of the received signal, and further scales the target Eb/N0 by this information rate scaling factor. The mobile station then compares the target Eb/N0 to a measured Eb/N0 of the received signal.