Patents by Inventor Quinn Li
Quinn Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097041Abstract: A thin film transistor, a semiconductor device having a thin film transistor and a method of fabricating a thin film transistor are provided. The thin film transistor includes a gate metal; a gate dielectric layer disposed on the gate metal; a semiconductor layer disposed on the gate dielectric layer; an interlayer dielectric disposed on the semiconductor layer and having a contact hole over the semiconductor layer; a source/drain metal disposed in the contact hole; a first liner disposed between the interlayer dielectric and the source/drain metal; and a second liner disposed between the first liner and the source/drain metal and being in contact with the semiconductor layer in the contact hole.Type: ApplicationFiled: November 23, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neil Quinn Murray, Hung-Wei Li, Mauricio MANFRINI, Sai-Hooi Yeong
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Patent number: 10628276Abstract: Aspects of the present invention provide an approach for integrated testing of gateway appliance software services. In an embodiment, a test request is received at a unit test framework installed on the gateway appliance. The unit test framework dynamically generates a set of stub code for processing the test request. This set of stub code executes target code (e.g., code that is being tested) of the software services. Results of the execution are verified to determine whether the code passes the test.Type: GrantFiled: June 29, 2018Date of Patent: April 21, 2020Assignee: International Business Machines CorporationInventors: Rahul S. Shinge, Eric Simon, Quinn Li
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Publication number: 20200004665Abstract: Aspects of the present invention provide an approach for integrated testing of gateway appliance software services. In an embodiment, a test request is received at a unit test framework installed on the gateway appliance. The unit test framework dynamically generates a set of stub code for processing the test request. This set of stub code executes target code (e.g., code that is being tested) of the software services. Results of the execution are verified to determine whether the code passes the test.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Rahul S. Shinge, Eric Simon, Quinn Li
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Patent number: 8580708Abstract: The present disclosure relates to cryoprotection of plants. The compositions and methods disclosed herein provide a means for protecting plants from frost or freeze damage or death due to sudden exposure to low temperature conditions. The present disclosure further relates to methods for providing cryoprotection to plants.Type: GrantFiled: June 17, 2008Date of Patent: November 12, 2013Assignee: Board of Trustees of the University of AlabamaInventors: David Francko, Kenneth G. Wilson, Qingshun Quinn Li, Maria Alejandra Equiza
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Patent number: 8582636Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.Type: GrantFiled: February 2, 2010Date of Patent: November 12, 2013Assignee: Broadcom CorporationInventors: Stephen Allpress, Quinn Li
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Patent number: 8121182Abstract: An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.Type: GrantFiled: December 11, 2006Date of Patent: February 21, 2012Assignee: Broadcom CorporationInventors: Steve A. Allpress, Quinn Li
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Publication number: 20100255991Abstract: The present disclosure relates to cryoprotection of plants. The compositions and methods disclosed herein provide a means for protecting plants from frost or freeze damage or death due to sudden exposure to low temperature conditions. The present disclosure further relates to methods for providing cryoprotection to plants.Type: ApplicationFiled: June 17, 2008Publication date: October 7, 2010Inventors: David A. Francko, Kenneth G. Wilson, Quinn Li, Maria Alejandra Equiza
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Publication number: 20100202507Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.Type: ApplicationFiled: February 2, 2010Publication date: August 12, 2010Inventors: Stephen Allpress, Quinn Li
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Patent number: 7656943Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.Type: GrantFiled: March 14, 2006Date of Patent: February 2, 2010Inventors: Stephen Allpress, Quinn Li
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Publication number: 20080159377Abstract: An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.Type: ApplicationFiled: March 6, 2008Publication date: July 3, 2008Inventors: Steve A. Allpress, Quinn Li
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Publication number: 20070140330Abstract: An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.Type: ApplicationFiled: December 11, 2006Publication date: June 21, 2007Inventors: Steve Allpress, Quinn Li
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Patent number: 7230982Abstract: This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For minimum-phase channels, the equalization is performed in a time-forward manner. For maximum-phase channels, the equalization is performed in a time-reversed manner. More specifically, for maximum-phase channels, the filter coefficients are computed based on the channel estimates reversed in time, and the filtering and equalization operations are performed with the received block of symbols in a time-reversed order. In the context of this invention, the term “minimum-phase channel” implies that the energy of the leading part of the channel profile is greater than the energy of the trailing part. The term “maximum-phase channel” implies that the energy of the leading part of the channel profile is less than the energy of the trailing part.Type: GrantFiled: January 31, 2006Date of Patent: June 12, 2007Assignee: Broadcom CorporationInventors: Steve A. Allpress, Quinn Li
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Patent number: 7151796Abstract: An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.Type: GrantFiled: September 4, 2001Date of Patent: December 19, 2006Assignee: Broadcom CorporationInventors: Steve A. Allpress, Quinn Li
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Publication number: 20060176949Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.Type: ApplicationFiled: March 14, 2006Publication date: August 10, 2006Inventors: Stephen Allpress, Quinn Li
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Publication number: 20060120446Abstract: This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For minimum-phase channels, the equalization is performed in a time-forward manner. For maximum-phase channels, the equalization is performed in a time-reversed manner. More specifically, for maximum-phase channels, the filter coefficients are computed based on the channel estimates reversed in time, and the filtering and equalization operations are performed with the received block of symbols in a time-reversed order. In the context of this invention, the term “minimum-phase channel” implies that the energy of the leading part of the channel profile is greater than the energy of the trailing part. The term “maximum-phase channel” implies that the energy of the leading part of the channel profile is less than the energy of the trailing part.Type: ApplicationFiled: January 31, 2006Publication date: June 8, 2006Inventors: Steve Allpress, Quinn Li
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Patent number: 7012957Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.Type: GrantFiled: August 27, 2001Date of Patent: March 14, 2006Assignee: Broadcom CorporationInventors: Stephen Allpress, Quinn Li
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Patent number: 7006563Abstract: This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For minimum-phase channels, the equalization is performed in a time-forward manner. For maximum-phase channels, the equalization is performed in a time-reversed manner. More specifically, for maximum-phase channels, the filter coefficients are computed based on the channel estimates reversed in time, and the filtering and equalization operations are performed with the received block of symbols in a time-reversed order. In the context of this invention, the term “minimum-phase channel” implies that the energy of the leading part of the channel profile is greater than the energy of the trailing part. The term “maximum-phase channel” implies that the energy of the leading part of the channel profile is less than the energy of the trailing part.Type: GrantFiled: August 27, 2001Date of Patent: February 28, 2006Assignee: Broadcom CorporationInventors: Steve A. Allpress, Quinn Li
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Patent number: 6721339Abstract: A transmitter for wireless communications provides multiple types of orthogonality to improve transmit diversity. Transmit diversity is improved by using both coding and carrier frequency orthogonality. Data to be transmitted is broken into four parallel channels. Two of the channels are transmitted on a first carrier signal and the other two channels are transmitted on a second carrier signal. Channels transmitted on the same carrier signal are provided with orthogonal codes so that they may be separated by a receiver. Channels transmitted on different carrier signals may be encoded with identical orthogonal codes. The modulated carrier signals are then transmitted using at least two antennas, where one antenna is used for each carrier.Type: GrantFiled: August 17, 1999Date of Patent: April 13, 2004Assignee: Lucent Technologies Inc.Inventors: Quinn Li, Nallepilli S. Ramesh
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Patent number: 6643280Abstract: A long code generator is disclosed that maintains a common long code state between a system with multiple spreading rates, such as a spreading rate equal to the chip rate (1×) and a spreading rate at a multiple of the chip rate (n×), such as three-times the chip rate (3×). An n× long code generator generates n bits for every clock pulse, where the clock operates at the system chip rate. n bits are generated for every clock period by having the long code mask value assume n values for each clock period. Thus, the long code mask value is changed at n times the chip rate, while the shift register is operated at the chip rate. Each of the long codes corresponding to the n long code mask values are multiplexed, for example, using an interlacing technique. The long code generator includes a conventional shift register, AND gate array, modulo-2 adder and clock.Type: GrantFiled: October 27, 1999Date of Patent: November 4, 2003Assignee: Lucent Technologies Inc.Inventors: Quinn Li, Nallepilli S. Ramesh
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Patent number: 6590873Abstract: The invention is a method for controlling power on multiple forward link communication channels by using multiple power control sub-channels, wherein each power control sub-channel is associated with a forward link communication channel to be power controlled. A fundamental power control sub-channel and a supplemental power control sub-channel are time multiplexed onto a reverse pilot channel. Transmitted over the fundamental power control sub-channel is a fundamental power control bit for indicating to a base station to increase or decrease its transmission power over a corresponding forward fundamental channel. Transmitted over the supplemental power control sub-channel is a supplemental power control bit for indicating to a base station to increase or decrease its transmission power over a corresponding forward supplemental channel. The pilot sub-channels are preferably separated by the fundamental and supplemental power control sub-channels for time diversity purposes.Type: GrantFiled: February 5, 1999Date of Patent: July 8, 2003Assignee: Lucent Technologies Inc.Inventors: Quinn Li, Martin Howard Meyers, John Minkoff, Xiao Cheng Wu