Patents by Inventor Qun Gao
Qun Gao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11958919Abstract: The present invention provides a “living” radical polymerization method for a vinyl monomer by near-infrared photothermal conversion. The method comprises irradiating a reactor with near-infrared light of 750-850 nm, wherein the reactor has a first chamber and a second chamber that are isolated from each other, the first chamber contains an organic solution of a near-infrared light responsive croconaine dye, and the second chamber is provided with a closed reaction flask containing a reaction solution, the reaction solution comprises a vinyl monomer, two or more of an ATRP initiator, an ATRP ligand, an ATRP catalyst, an RAFT reagent, a thermal initiator, and an additive, and an organic solvent; and the near-infrared light responsive dye converts the near-infrared light into heat energy, by which the reactor is heated to 50-100° C. to polymerize the monomer in the reaction solution, to obtain polymers with controlled molecular weights and molecular weight distributions.Type: GrantFiled: January 8, 2020Date of Patent: April 16, 2024Assignee: SOOCHOW UNIVERSITYInventors: Lifen Zhang, Qun Gao, Zhenping Cheng, Kai Tu, Haihui Li, Lan Yao, Xiulin Zhu
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Publication number: 20240067036Abstract: Disclosed is a charging station capable of realizing mutual capacity aid, which comprises a plurality of charging units, a power bus and a mutual capacity aid bus. Each charging unit is powered by the power bus, and each charging unit provides mutual aid capacity for another charging unit through the mutual capacity aid bus or receives mutual aid capacity from other charging units through the mutual capacity aid bus. The charging station can realize rapid charging of electric vehicles, and can also realize mutual capacity aid.Type: ApplicationFiled: June 4, 2021Publication date: February 29, 2024Applicants: JIANGSU ELECTRIC POWER RESEARCH INSTITUTE CO., LTD., STATE GRID JIANGSU ELECTRIC POWER CO., LTD. RESEARCH INSTITUTEInventors: Tiankui SUN, Yubo YUAN, Mingming SHI, Xin FANG, Jinggang YANG, Shuyi ZHUANG, Xiaodong YUAN, Chenyu ZHANG, Lei GAO, Peng LI, Yaojia MA, Shu CHEN, Jing CHEN, Qun LI, Jian LIU
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Patent number: 11691089Abstract: Provided are a vacuum rectification tower with a satellite-type tower kettle and a vacuum rectification method for atmospheric pressure residual oil. The vacuum rectification tower includes a satellite-surrounded vacuum tower kettle and a rectifying section; the satellite-surrounded vacuum tower kettle includes a main tower kettle and a plurality of sub-reactors arranged outside the main tower kettle in a satellite-surrounded mode; the main tower kettle is provided with a first outlet and a plurality of spray inlets, and a top portion of the main tower kettle has an opening; the sub-reactor is provided with a second outlet and a first inlet, the spray inlets are connected with the second outlets of each sub-reactor in a one-to-one correspondence, and the first outlet is connected with the first inlets.Type: GrantFiled: May 28, 2021Date of Patent: July 4, 2023Assignees: BEIJING JIESENCHUANGXIN SCIENCE & TECHNOLOGY DEVELOPMENT CO. LTD.Inventors: Qikai Zhang, Penghui Xu, Qun Gao
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Publication number: 20220415908Abstract: Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.Type: ApplicationFiled: July 14, 2021Publication date: December 29, 2022Inventors: Guangyu Huang, Dipanjan Basu, Meng-Wei Kuo, Randy Koval, Henok Mebrahtu, Minsheng Wang, Jie Li, Fei Wang, Qun Gao, Xingui Zhang, Guanjie Li
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Publication number: 20220305400Abstract: Provided are a vacuum rectification tower with a satellite-type tower kettle and a vacuum rectification method for atmospheric pressure residual oil. The vacuum rectification tower includes a satellite-surrounded vacuum tower kettle and a rectifying section; the satellite-surrounded vacuum tower kettle includes a main tower kettle and a plurality of sub-reactors arranged outside the main tower kettle in a satellite-surrounded mode; the main tower kettle is provided with a first outlet and a plurality of spray inlets, and a top portion of the main tower kettle has an opening; the sub-reactor is provided with a second outlet and a first inlet, the spray inlets are connected with the second outlets of each sub-reactor in a one-to-one correspondence, and the first outlet is connected with the first inlets.Type: ApplicationFiled: May 28, 2021Publication date: September 29, 2022Inventors: Qikai ZHANG, Penghui XU, Qun GAO
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Patent number: 11420175Abstract: The present disclosure provides a differential hydrogenation reaction apparatus. The apparatus comprises a mixing vessel, a plurality of microreactors and a raw material conveying device, and the mixing vessel is provided with reaction product inlets; each microreactor is used as a hydrogenation reaction place and is provided with a liquid phase reaction raw material inlet and a reaction product outlet, each reaction product outlet is connected with the corresponding reaction product inlet, the plurality of microreactors are divided into one group or a plurality of groups which are arranged in parallel, and each group comprises at least one microreactor arranged in parallel; and the raw material conveying device is arranged on a feeding pipeline of the liquid phase reaction raw material inlet. The problems of high pressure unsafety and non-equilibrium in the hydrogenation reaction process can be effectively solved by adopting the reaction apparatus.Type: GrantFiled: November 23, 2020Date of Patent: August 23, 2022Assignees: BEIJING JIENSENCHUANGXIN SCIENCE & TECHNOLOGY DEVELOPMENT CO., LTD.Inventors: Qikai Zhang, Penghui Xu, Qun Gao
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Publication number: 20220112316Abstract: The present invention provides a “living” radical polymerization method for a vinyl monomer by near-infrared photothermal conversion. The method comprises irradiating a reactor with near-infrared light of 750-850 nm, wherein the reactor has a first chamber and a second chamber that are isolated from each other, the first chamber contains an organic solution of a near-infrared light responsive croconaine dye, and the second chamber is provided with a closed reaction flask containing a reaction solution, the reaction solution comprises a vinyl monomer, two or more of an ATRP initiator, an ATRP ligand, an ATRP catalyst, an RAFT reagent, a thermal initiator, and an additive, and an organic solvent; and the near-infrared light responsive dye converts the near-infrared light into heat energy, by which the reactor is heated to 50-100° C. to polymerize the monomer in the reaction solution, to obtain polymers with controlled molecular weights and molecular weight distributions.Type: ApplicationFiled: January 8, 2020Publication date: April 14, 2022Inventors: Lifen ZHANG, Qun GAO, Zhenping CHENG, Kai TU, Haihui LI, Lan YAO, Xiulin ZHU
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Publication number: 20210154638Abstract: The present disclosure provides a differential hydrogenation reaction apparatus. The apparatus comprises a mixing vessel, a plurality of microreactors and a raw material conveying device, and the mixing vessel is provided with reaction product inlets; each microreactor is used as a hydrogenation reaction place and is provided with a liquid phase reaction raw material inlet and a reaction product outlet, each reaction product outlet is connected with the corresponding reaction product inlet, the plurality of microreactors are divided into one group or a plurality of groups which are arranged in parallel, and each group comprises at least one microreactor arranged in parallel; and the raw material conveying device is arranged on a feeding pipeline of the liquid phase reaction raw material inlet. The problems of high pressure unsafety and non-equilibrium in the hydrogenation reaction process can be effectively solved by adopting the reaction apparatus.Type: ApplicationFiled: November 23, 2020Publication date: May 27, 2021Inventors: Qikai ZHANG, Penghui XU, Qun GAO
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Patent number: 10886178Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.Type: GrantFiled: August 22, 2018Date of Patent: January 5, 2021Assignee: GLOBALFOUNDRIES INC.Inventors: Tek Po Rinus Lee, Annie Levesque, Qun Gao, Hui Zang, Rishikesh Krishnan, Bharat Krishnan, Curtis Durfee
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Patent number: 10832965Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.Type: GrantFiled: January 11, 2018Date of Patent: November 10, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Yiheng Xu, Haiting Wang, Qun Gao, Scott Beasor, Kyung Bum Koo, Ankur Arya
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Patent number: 10727133Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.Type: GrantFiled: September 18, 2018Date of Patent: July 28, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Qun Gao, Balaji Kannan, Shesh Mani Pandey, Haiting Wang
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Patent number: 10636894Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.Type: GrantFiled: March 9, 2018Date of Patent: April 28, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti, Yi Qi, Wei Hong, Yongjun Shi, Jae Gon Lee, Chun Yu Wong
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Publication number: 20200091005Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.Type: ApplicationFiled: September 18, 2018Publication date: March 19, 2020Inventors: Qun Gao, Balaji Kannan, Shesh Mani Pandey, Haiting Wang
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Patent number: 10593555Abstract: The manufacture of a FinFET device includes the formation of a composite sacrificial gate. The composite sacrificial gate includes a sacrificial gate layer such as a layer of amorphous silicon, and an etch selective layer such as a layer of silicon germanium. The etch selective layer, which underlies the sacrificial gate layer, enables the formation of a gate cut opening having a controlled critical dimension that extends through the composite sacrificial gate.Type: GrantFiled: March 20, 2018Date of Patent: March 17, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Qun Gao, Naved Siddiqui, Ankur Arya, John R Sporre
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Publication number: 20200066593Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.Type: ApplicationFiled: August 22, 2018Publication date: February 27, 2020Inventors: Tek Po Rinus LEE, Annie LEVESQUE, Qun GAO, Hui ZANG, Rishikesh KRISHNAN, Bharat KRISHNAN, Curtis DURFEE
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Patent number: 10529831Abstract: At least one method, apparatus and system providing semiconductor devices comprising a semiconductor substrate; a first fin and a second fin on the semiconductor substrate; a first epitaxial formation on the first fin and having an inner surface oriented toward the second fin and an outer surface oriented away from the second fin; a second epitaxial formation on the second fin and having an inner surface oriented toward the first fin and an outer surface oriented away from the first fin; and a conformal dielectric layer on at least portions of the inner and outer surfaces of the first epitaxial formation, on at least portions of the inner and outer surfaces of the first epitaxial formation and the second epitaxial formation, and merged between the inner surface of the first epitaxial formation and inner surface of the second epitaxial formation.Type: GrantFiled: August 3, 2018Date of Patent: January 7, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Qun Gao, Matthew W. Stoker, Haigou Huang
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Patent number: 10453754Abstract: The present disclosure is directed to various methods of diffusing contact extension dopants in a transistor device and the resulting devices. One illustrative method includes forming a first contact opening between two adjacent gate structures formed above a first fin, the first contact opening exposing a first region of the first fin, forming a first contact recess in the first region, forming a first doped liner in the first contact recess, performing an anneal process to diffuse dopants from the first doped liner into the first fin to form a first doped contact extension region in the first fin, and performing a first epitaxial growth process to form a first source/drain region in the first contact recess.Type: GrantFiled: June 28, 2018Date of Patent: October 22, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Jianwei Peng, Haigou Huang, Qun Gao, Xin Wang
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Publication number: 20190305105Abstract: A method for controlling the gate length within a FinFET device to increase power performance and the resulting device are provided. Embodiments include forming a vertical gate to extend over a plurality of fins; depositing a respective oxide layer over each of a plurality of skirt regions formed at respective points of intersection of the vertical gate with the plurality of fins; and oxidizing each oxide layer to form a plurality of oxidized gate skirts.Type: ApplicationFiled: April 2, 2018Publication date: October 3, 2019Inventors: Qun GAO, Christopher NASSAR, Sugirtha KRISHNAMURTHY, Domingo Antonio FERRER LUPPI, John SPORRE, Shahab SIDDIQUI, Beth BAUMERT, Abu ZAINUDDIN, Jinping LIU, Tae Jeong LEE, Luigi PANTISANO, Heather LAZAR, Hui ZANG
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Publication number: 20190295852Abstract: The manufacture of a FinFET device includes the formation of a composite sacrificial gate. The composite sacrificial gate includes a sacrificial gate layer such as a layer of amorphous silicon, and an etch selective layer such as a layer of silicon germanium. The etch selective layer, which underlies the sacrificial gate layer, enables the formation of a gate cut opening having a controlled critical dimension that extends through the composite sacrificial gate.Type: ApplicationFiled: March 20, 2018Publication date: September 26, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Qun GAO, Naved SIDDIQUI, Ankur ARYA, John R. Sporre
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Publication number: 20190280105Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.Type: ApplicationFiled: March 9, 2018Publication date: September 12, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti, Yi Qi, Wei Hong, Yongjun Shi, Jae Gon Lee, Chun Yu Wong