Patents by Inventor Qunyi YANG

Qunyi YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230169012
    Abstract: An electronic device includes remapping hardware, a processor, and a Northbridge IC. The remapping hardware converts a virtual address included in an unconverted DMA request into a physical address. The processor executes software to configure the remapping hardware. The Northbridge IC sends the physical address to the processor. When the software changes the configuration of the remapping hardware, the remapping hardware outputs a data draining request to the Northbridge IC. When the Northbridge IC receives the data draining request at a first time, the Northbridge IC suspends unconverted DMA requests after the first time until a second time, and outputs a first data draining response to the remapping hardware at the second time. The remapping hardware receives the first data draining response and notifies the processor that the data draining request has been completed.
    Type: Application
    Filed: October 19, 2022
    Publication date: June 1, 2023
    Inventors: Yang JIAO, Qunyi YANG, Jin XIANG, Xinglin GUI, Tingli CUI
  • Publication number: 20230127938
    Abstract: A method and a device for rapidly searching a cache are provided. The method for rapidly searching a cache includes: translating a source identifier (SID) to a domain identifier (DID) according to an extended flag from the software by searching a context cache, wherein the extended flag indicates that a current context entry stored in the context cache is a normal context entry or an extended context entry.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 27, 2023
    Inventors: Qunyi YANG, Tingli CUI, Xinglin GUI
  • Publication number: 20230128405
    Abstract: An electronic device is provided. The electronic device includes a memory and an integrated circuit. The integrated circuit includes an address remapping unit. The memory includes multiple memory pages. The integrated circuit converts multiple virtual addresses into multiple physical addresses in sequence. The address remapping unit prefetches a first physical address corresponding to a first virtual address if a second virtual address exceeds a preset offset. The first virtual address is in a different memory page from the second virtual address. The second virtual address is currently processed. The multiple virtual addresses include the first and second virtual addresses.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 27, 2023
    Inventors: Qunyi YANG, Yang JIAO, Jin XIANG, Tingli CUI, Xinglin GUI
  • Publication number: 20230125344
    Abstract: A method for remapping a virtual address to a physical address is provided. The method is used in an address remapping unit and includes: receiving, by a remapping processing unit of the address remapping unit, a remapping request, decoding the remapping request and determining whether the remapping request has a direct memory access (DMA) remapping request; and executing, by the remapping processing unit, a remapping procedure: translating a virtual address corresponding to the remapping request to a physical address, when the remapping request has the DMA remapping request.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 27, 2023
    Inventors: Qunyi YANG, Peng SHEN, Fan YANG
  • Patent number: 11341062
    Abstract: An acceleration technology for accessing system memory, which provides translation agent hardware that calculates the physical address of the system memory based on an access request issued from the device end. The translation agent hardware has a cache memory that stores information to speed up the calculation of the physical address. Each cache line corresponds to a last-recently used (LRU) index value, and the cache line with the greatest LRU index value is preferentially released to be reassigned. A counter counts a count value to show an isochronous caching demand. LRU index values of cache lines assigned to non-isochronous caching are kept not lower than the count value, and thereby isochronous caching takes precedence over non-isochronous caching.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 24, 2022
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Qunyi Yang, Hui Wu, Tingli Cui
  • Publication number: 20220004505
    Abstract: An acceleration technology for accessing system memory, which provides translation agent hardware that calculates the physical address of the system memory based on an access request issued from the device end. The translation agent hardware has a cache memory that stores information to speed up the calculation of the physical address. Each cache line corresponds to a last-recently used (LRU) index value, and the cache line with the greatest LRU index value is preferentially released to be reassigned. A counter counts a count value to show an isochronous caching demand. LRU index values of cache lines assigned to non-isochronous caching are kept not lower than the count value, and thereby isochronous caching takes precedence over non-isochronous caching.
    Type: Application
    Filed: September 9, 2020
    Publication date: January 6, 2022
    Inventors: Qunyi YANG, Hui WU, Tingli CUI