Patents by Inventor Quy Hoang
Quy Hoang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11863697Abstract: Provided is an electronic device including: a housing; a camera module oriented in a first direction inside the housing; a camera window arranged in front of the camera module in the first direction; a cover including an opening into which the camera window is insertable, the cover coupled to the housing; and a window frame supporting the camera window and mounted on the cover. The window frame includes: a frame body including a support portion arranged in the opening and supporting the camera window, and a mounting portion extending from the support portion in a second direction that is perpendicular to the first direction and overlapped by the cover in the first direction; a retention member retaining a first gap between the mounting portion and the cover in the first direction; and a waterproof body configured to be elastically deformed while arranged between the mounting portion and the cover.Type: GrantFiled: October 29, 2021Date of Patent: January 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoang Nguyen Van, Tri Bui Dac, Tung Dong Manh, Quy Hoang Kim, Kyoungsun Lee, Thang Ngo Van, Chien Nguyen Quoc, Thanh Tran Quoc
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Publication number: 20220053076Abstract: Provided is an electronic device including: a housing; a camera module oriented in a first direction inside the housing; a camera window arranged in front of the camera module in the first direction; a cover including an opening into which the camera window is insertable, the cover coupled to the housing; and a window frame supporting the camera window and mounted on the cover. The window frame includes: a frame body including a support portion arranged in the opening and supporting the camera window, and a mounting portion extending from the support portion in a second direction that is perpendicular to the first direction and overlapped by the cover in the first direction; a retention member retaining a first gap between the mounting portion and the cover in the first direction; and a waterproof body configured to be elastically deformed while arranged between the mounting portion and the cover.Type: ApplicationFiled: October 29, 2021Publication date: February 17, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoang NGUYEN VAN, Tri BUI DAC, Tung DONG MANH, Quy HOANG KIM, Kyoungsun LEE, Thang NGO VAN, Chien NGUYEN QUOC, Thanh TRAN QUOC
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Patent number: 11068278Abstract: An information handling system includes a dual in-line memory module (DIMM) coupled to a memory controller via a memory channel. A processor during a first in time boot process of the information handling system determines a first environmental condition of the information handling system, and initializes the memory controller and the DIMM to determine a first set of initialization parameters for the memory controller and the DIMM. During a second in time boot process of the information handling system, the processor determines if a second environmental condition is different than the first environmental condition, if the second environmental condition is not different then to continue the second in time boot process without initializing the memory controller and the DIMM, and if the second environmental condition is different then to initialize the memory controller and the DIMM to determine a second set of initialization parameters for the memory controller and the DIMM.Type: GrantFiled: October 18, 2019Date of Patent: July 20, 2021Assignee: Dell Products L.P.Inventors: Mark Shutt, Wei G Liu, Quy Hoang, Andy Butcher
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Patent number: 11016835Abstract: An information handling system includes a dual in-line memory module (DIMM) coupled to a memory controller. The memory controller provides interrupts to a processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor that receives the interrupts, accumulates a count of the interrupts, and provides an error indication when the count exceeds an error threshold. In accumulating the count, the failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when a training coefficient for the DIMM is greater than a deviation threshold, and has a second value when the training coefficient for the DIMM is less than the deviation threshold.Type: GrantFiled: October 18, 2019Date of Patent: May 25, 2021Assignee: Dell Products L.P.Inventors: Quy Hoang, Wei G Liu, Andy Butcher, Mark Shutt
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Publication number: 20210117206Abstract: An information handling system includes a dual in-line memory module (DIMM) coupled to a memory controller via a memory channel. A processor during a first in time boot process of the information handling system determines a first environmental condition of the information handling system, and initializes the memory controller and the DIMM to determine a first set of initialization parameters for the memory controller and the DIMM. During a second in time boot process of the information handling system, the processor determines if a second environmental condition is different than the first environmental condition, if the second environmental condition is not different then to continue the second in time boot process without initializing the memory controller and the DIMM, and if the second environmental condition is different then to initialize the memory controller and the DIMM to determine a second set of initialization parameters for the memory controller and the DIMM.Type: ApplicationFiled: October 18, 2019Publication date: April 22, 2021Inventors: Mark Shutt, Wei G Liu, Quy Hoang, Andy Butcher
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Publication number: 20210117257Abstract: An information handling system includes a dual in-line memory module (DIMM) coupled to a memory controller. The memory controller provides interrupts to a processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor that receives the interrupts, accumulates a count of the interrupts, and provides an error indication when the count exceeds an error threshold. In accumulating the count, the failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when a training coefficient for the DIMM is greater than a deviation threshold, and has a second value when the training coefficient for the DIMM is less than the deviation threshold.Type: ApplicationFiled: October 18, 2019Publication date: April 22, 2021Inventors: Quy Hoang, Wei G Liu, Andy Butcher, Mark Shutt
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Patent number: 8245053Abstract: Methods and systems for binding a removable trusted platform module (TPM) subsystem module to an information handling system to provide a core root of trust for the information handling system without requiring soldering down or other hard and permanent (non-removable) attachment of a TPM device to the information handling system planar (e.g., motherboard). The removable TPM subsystem module may be a plug-in module that may be removed from the information handling system planar (e.g., motherboard), while at the same time maintaining the transitive chain of trust, and being capable of remotely attesting its trusted state. An information handling system platform may be provided that has the capability and flexibility of supporting multiple TPMs on the same system planar.Type: GrantFiled: March 10, 2009Date of Patent: August 14, 2012Assignee: Dell Products, Inc.Inventors: Quy Hoang, Mukund P. Khatri, Pankaj Bishnoi
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Patent number: 7877639Abstract: The present disclosure further relates to information handling systems with failover support for booting an embedded hypervisor, the information handling system. For example, an information handling system with failover support may comprise a processor; one or more applications configured to be executed, at least in part, by the processor; a memory communicatively coupled to the processor and comprising a basic input/output system (BIOS), the BIOS comprising a BIOS universal serial bus (USB) driver, the BIOS USB driver comprising a mass storage device driver; a primary internal embedded hypervisor non-volatile memory (NVM) card communicatively coupled to the memory, the first NVM card comprising a first bootable hypervisor image; and a back up internal embedded hypervisor NVM card communicatively coupled to the memory, the second NVM card comprising a second bootable hypervisor image.Type: GrantFiled: November 6, 2008Date of Patent: January 25, 2011Assignee: Dell Products L.P.Inventors: Quy Hoang, Wei Liu
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Publication number: 20100235648Abstract: Methods and systems for binding a removable trusted platform module (TPM) subsystem module to an information handling system to provide a core root of trust for the information handling system without requiring soldering down or other hard and permanent (non-removable) attachment of a TPM device to the information handling system planar (e.g., motherboard). The removable TPM subsystem module may be a plug-in module that may be removed from the information handling system planar (e.g., motherboard), while at the same time maintaining the transitive chain of trust, and being capable of remotely attesting its trusted state. An information handling system platform may be provided that has the capability and flexibility of supporting multiple TPMs on the same system planar.Type: ApplicationFiled: March 10, 2009Publication date: September 16, 2010Inventors: Quy Hoang, Mukund P. Khatri, Pankaj Bishnoi
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Publication number: 20100115257Abstract: The present disclosure further relates to information handling systems with failover support for booting an embedded hypervisor, the information handling system. For example, an information handling system with failover support may comprise a processor; one or more applications configured to be executed, at least in part, by the processor; a memory communicatively coupled to the processor and comprising a basic input/output system (BIOS), the BIOS comprising a BIOS universal serial bus (USB) driver, the BIOS USB driver comprising a mass storage device driver; a primary internal embedded hypervisor non-volatile memory (NVM) card communicatively coupled to the memory, the first NVM card comprising a first bootable hypervisor image; and a back up internal embedded hypervisor NVM card communicatively coupled to the memory, the second NVM card comprising a second bootable hypervisor image.Type: ApplicationFiled: November 6, 2008Publication date: May 6, 2010Applicant: DELL PRODUCTS L.P.Inventors: Quy Hoang, Wei Liu