Abstract: An information handling system includes a motherboard installed within a chassis, a first backplane coupled to the motherboard, a second backplane coupled to the motherboard. The first backplane is located in a front side of the chassis, and is configured to receive first add-in modules from the front of the chassis. The second backplane is located in a middle portion of the chassis, and is configured to receive second add-in modules. The second add-in modules are positioned above DIMMs installed in the motherboard.

Abstract: An information handling system includes a memory controller coupled to a first memory device and to a second memory device. The first and second memory devices are configured to receive memory access requests addressed based upon a device physical address (DPA) space of the memory controller. The memory controller incudes a page redirection table having an entry for each page of a host physical address (HPA) space of the information handling system corresponding with the pages of the DPA space. Each entry of the page redirection table associates the particular page of the HPA space with a page within the DPA space. The memory controller receives memory access requests addressed with HPAs from a host processor, and fulfills the memory access requests from a selected one of the first and second memory devices based upon DPAs determined from the entries of the page redirection table.

Abstract: An information handling system includes a first processor core that receives a first System Management Interrupt (SMI) event, and synchronizes entry into a System Management Mode (SMM) with second and third processor cores. In response to the first, second, and third processor cores being in the SMM, the first processor executes a first SMI handler to service the first SMI. While the first, second, and third processor core are in the SMM, the second processor core monitors for a high priority SMI event. In response to a detection of the high priority SMI event, the second processor core executes a second SMI handler to service the high priority SMI event.