Abstract: Embodiments of an active power switch topology for a switching regulator are provided herein. The embodiments of the active power switch topology use two or more active power switches in parallel instead of a single active power switch, as found in conventional implementations. The active power switches are controlled such that they turn-on and -off in a manner that reduces parasitic voltage spikes associated with conventional switching regulators, while not degrading efficiency or other parameters associated with the switching regulator. The active power switch topology can be beneficially used within many switching regulators (e.g., buck, boost, or buck-boost) and, in particular, within hard-switched switching regulators that include active power switches integrated on chip.

Abstract: Embodiments of an active power switch topology for a switching regulator are provided herein. The embodiments of the active power switch topology use two or more active power switches in parallel instead of a single active power switch, as found in conventional implementations. The active power switches are controlled such that they turn-on and -off in a manner that reduces parasitic voltage spikes associated with conventional switching regulators, while not degrading efficiency or other parameters associated with the switching regulator. The active power switch topology can be beneficially used within many switching regulators (e.g., buck, boost, or buck-boost) and, in particular, within hard-switched switching regulators that include active power switches integrated on chip.