Patents by Inventor Quynh Tran

Quynh Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8019186
    Abstract: The invention relates to a photonic crystal circuit comprising a guide produced in a photonic crystal membrane on the surface of a substrate and a mode adapter coupled to said guide, wherein the membrane includes a central point constituting the mode adapter having a section gradient as termination of said guide, said point being suspended so as to allow the propagation of modes in a symmetrical manner. It also relates to an optical system incorporating said circuit coupled to an optical fiber.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: September 13, 2011
    Assignee: Thales
    Inventors: Sylvain Combrie, Nguyen Vy Quynh Tran, Alfredo De Rossi
  • Publication number: 20100272387
    Abstract: The invention relates to a photonic crystal circuit comprising a guide produced in a photonic crystal membrane on the surface of a substrate and a mode adapter coupled to said guide, wherein the membrane includes a central point constituting the mode adapter having a section gradient as termination of said guide, said point being suspended so as to allow the propagation of modes in a symmetrical manner. It also relates to an optical system incorporating said circuit coupled to an optical fiber.
    Type: Application
    Filed: July 8, 2009
    Publication date: October 28, 2010
    Applicant: Thales
    Inventors: Sylvain Combrie, Nguyen Vy Quynh Tran, Alfredo De Rossi
  • Publication number: 20100046572
    Abstract: The invention relates to a photon extractor comprising a photonic-crystal-based membrane having a plane defined by two perpendicular directions, comprising an array of features and a cavity devoid of features, from which photons may be extracted, characterized in that the membrane comprises at least one region close to the cavity, said region having features distributed with a double periodicity (a1, 2a1, a2, 2a2) along at least one direction.
    Type: Application
    Filed: July 8, 2009
    Publication date: February 25, 2010
    Applicant: Thales
    Inventors: Alfredo De Rossi, Sylvain Combrie, Nguyen Vy Quynh Tran
  • Publication number: 20090214843
    Abstract: An epitaxial silicon wafer is provided with a thickness in the area adjacent the edge that is greater or less than the thickness adjacent the center. The wafer may be manufactured by a method wherein one or more process parameters are adjusted during deposition of epitaxial layer to control the edge thickness.
    Type: Application
    Filed: December 23, 2008
    Publication date: August 27, 2009
    Applicant: Siltronic Corporation
    Inventors: Kevin Lite, Quynh Tran
  • Publication number: 20090215202
    Abstract: An epitaxial silicon wafer is produced with a resistivity in the area adjacent the edge that is greater or less than the resistivity adjacent the center. The wafer may be manufactured by a method wherein one or more process parameters are adjusted during deposition of epitaxial layer to control the edge resistivity. Such process parameters may include using a non-homogeneous temperature and/or a process reactant gas flow across the front surface of the wafer.
    Type: Application
    Filed: December 23, 2008
    Publication date: August 27, 2009
    Applicant: Siltronic Corporation
    Inventors: Kevin Lite, Quynh Tran