Abstract: A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces.

Abstract: A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces.

Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier. The conductive structure can include a base and a plurality of interconnections extending continuously away from the base toward the carrier. The microelectronic element can be positioned between at least two adjacent interconnections of the plurality of interconnections. The conductive structure may be bonded to the carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The plurality of interconnections and the microelectronic element may be encapsulated. The carrier may be removed to expose free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and bond pads of the microelectronic element may be conductively connected with terminals of the microelectronic package. The conductive structure may be patterned to form external contacts.

Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier. The conductive structure can include a base and a plurality of interconnections extending continuously away from the base toward the carrier. The microelectronic element can be positioned between at least two adjacent interconnections of the plurality of interconnections. The conductive structure may be bonded to the carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The plurality of interconnections and the microelectronic element may be encapsulated. The carrier may be removed to expose free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and bond pads of the microelectronic element may be conductively connected with terminals of the microelectronic package. The conductive structure may be patterned to form external contacts.

Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package.

Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package.

Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

Abstract: A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.

Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

Abstract: A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.

Abstract: A wire bond design integrated circuit with a substrate having a front side and an opposing back side. Circuitry is disposed on the font side. Electrically conductive vias are disposed through the substrate from the front side to the back side, and are electrically connected to the circuitry such that the electrically conductive vias provide power and ground services only for the circuitry. Bonding pads are disposed on the front side, and are electrically connected to the circuitry such that the bonding pads provide signal communication only for the circuitry.

Abstract: A packaged integrated circuit having a thermal pathway to exhaust heat from the integrated circuit. The integrated circuit is disposed on a package substrate, with an encapsulant disposed around the integrated circuit. A heat sink is disposed at least partially within the encapsulant, with at least a portion of one surface of the heat sink exposed outside of the encapsulant. The integrated circuit has an uppermost passivation layer, where the passivation layer is not electrically conductive, with a port disposed in the passivation layer. The port extends completely through the passivation layer to expose an underlying layer. A thermal pathway is disposed at least partially within the port, and makes thermal contact to both the underlying layer and the heat sink. The thermal transfer rate of the thermal pathway is greater than the thermal transfer rate either the passivation layer or the encapsulant.

Abstract: A semiconductor device includes a semiconductor die mounted over a package substrate. The die has a bond pad located thereover. A stud bump consisting substantially of a first metal is located on the bond pad. A wire consisting substantially of a different second metal is bonded to the stud bump.

Abstract: A wire bond design integrated circuit with a substrate having a front side and an opposing back side. Circuitry is disposed on the font side. Electrically conductive vias are disposed through the substrate from the front side to the back side, and are electrically connected to the circuitry such that the electrically conductive vias provide power and ground services only for the circuitry. Bonding pads are disposed on the front side, and are electrically connected to the circuitry such that the bonding pads provide signal communication only for the circuitry.

Abstract: A packaged integrated circuit having a thermal pathway to exhaust heat from the integrated circuit. The integrated circuit is disposed on a package substrate, with an encapsulant disposed around the integrated circuit. A heat sink is disposed at least partially within the encapsulant, with at least a portion of one surface of the heat sink exposed outside of the encapsulant. The integrated circuit has an uppermost passivation layer, where the passivation layer is not electrically conductive, with a port disposed in the passivation layer. The port extends completely through the passivation layer to expose an underlying layer. A thermal pathway is disposed at least partially within the port, and makes thermal contact to both the underlying layer and the heat sink. The thermal transfer rate of the thermal pathway is greater than the thermal transfer rate either the passivation layer or the encapsulant.

Abstract: A semiconductor device includes a semiconductor die mounted over a package substrate. The die has a bond pad located thereover. A stud bump consisting substantially of a first metal is located on the bond pad. A wire consisting substantially of a different second metal is bonded to the stud bump.