Patents by Inventor Qwai Hoong Low

Qwai Hoong Low has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing an electronic device package
    Patent number: 8869389
    Abstract: An electronic device package 100 comprising a lead frame 105 having at least one lead 110 with a notch 205. The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: October 28, 2014
    Assignee: LSI Corporation
    Inventors: Larry Golick, Qwai Hoong Low, John W. Osenbach, Matthew E. Stahley
  • Lead frame design to improve reliability
    Patent number: 8334467
    Abstract: An electronic device package 100 comprising a lead frame 150 having at least one lead 110 with a notch 205. The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: December 18, 2012
    Assignee: LSI Corporation
    Inventors: Larry W. Golick, Qwai Hoong Low, John W. Osenbach, Matthew E. Stahley
  • LEAD FRAME DESIGN TO IMPROVE RELIABILITY
    Publication number: 20100319987
    Abstract: An electronic device package 100 comprising a lead frame having at least one lead 110 with a notch 205. The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.
    Type: Application
    Filed: June 17, 2009
    Publication date: December 23, 2010
    Applicant: LSI Corporation
    Inventors: Larry W. Golick, Qwai Hoong Low, John W. Osenbach, Matthew E. Stahley
  • Multiple layer tape ball grid array package
    Patent number: 6285077
    Abstract: A package for an integrated circuit is disclosed. The package comprises two layers (a top layer and a bottom layer) of flexible tape, each of which has a top surface and a bottom surface, with metal traces on the top surface. A die is mounted on top of the two layers and wire bonds connect bond pads on the die to metal traces on each of the two flexible tapes. The metal traces are routed along the top surfaces of the flexible tapes and are coupled to solder balls through holes in the tapes. These solder balls are mounted along the bottom of the package and serve as the electrical interface to a printed circuit board. Additional holes in the bottom layer tape allow solder balls to extend through the bottom layer tape so that they may be electrically coupled to traces on the top layer tape.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: September 4, 2001
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Allen Lim, Qwai Hoong Low