Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a compensation capacitor that stores a compensation voltage during a calibration phase, and applies the stored compensation voltage to a compensation input of the compensation circuit of the amplifier during a measurement phase. Feedback from a source of the transistor controls the output of the differential amplifier to maintain a standard voltage across a resistive memory element connected to the source during measurement of the resistance of the resistive memory element, and the compensation circuit improves the accuracy of the voltage across the resistive memory element by compensating for an offset voltage of the differential amplifier.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: A simple method and device for accurately measuring flash memory cell current. The sensing scheme comprises an integrator, an analog to digital converter, and a digital to analog converter. The method comprises the acts of applying an input current and a feedback output current to a summer, integrating the resulting summer output over time, passing the integrated output to a clocked comparator, outputting a comparator output which controls a feedback circuit that keeps the integrator's voltage at the same level as a reference voltage, and outputting a digital average current to a counter. Delta sigma modulation (averaging) is employed to cancel out noise that would otherwise affect the cell current measurement.

Abstract: A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a switching point modulation circuit coupled to input logic and configured to modulate the periodic output signal from the input logic such that the periodic output signal is centered about a known voltage signal, such as a switching point voltage signal.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: A pair of self-biased differential amplifiers having a non-symmetrical topology are combined to provide a self-biased differential amplifier having a symmetrical topology. Each of the combined differential amplifiers includes a pair of transistors coupled to each other as a current mirror. The current mirror transistors are coupled in series with a respective one of a pair of differential input transistors. A current source transistor is coupled to the differential input transistors, and it is self-biased by one of the current mirror transistors.

Abstract: A circuit for reducing a mismatch between a reference path to which a reference voltage is applied and an intensity path to which an intensity voltage is applied from an active pixel sensor comprises a first and a second pair of switches and a processing circuit. The first pair of switches couple an intensity input node to which the intensity voltage is applied to a first output node and couple a reference input node to which the reference voltage is applied to a second output node during a first operating period. The second pair of switches couple the intensity input node to the second output node and couple the reference input node to the first output node during a second operating period. A polarity reversing circuit is included in the processing circuit for coupling the first and second output nodes to the processing circuit with one polarity during the first operating period and in a reverse polarity during the second operating period.

Abstract: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.

Abstract: An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a compensation capacitor that stores a compensation voltage during a calibration phase, and applies the stored compensation voltage to a compensation input of the compensation circuit of the amplifier during a measurement phase. Feedback from a source of the transistor controls the output of the differential amplifier to maintain a standard voltage across a resistive memory element connected to the source during measurement of the resistance of the resistive memory element, and the compensation circuit improves the accuracy of the voltage across the resistive memory element by compensating for an offset voltage of the differential amplifier.

Abstract: An integrated charge sensing scheme for sensing the resistance of a resistive memory element is described. The current through a resistive memory cell is used to charge a capacitor coupled to a digit line. The voltage on the capacitor, which corresponds to the voltage on the digit line, is applied to one input of a comparator. When the voltage on the bit line exceeds a predetermined fixed voltage applied to the second input to the comparator less an offset, the comparator switches logic state, charge is drawn off from the capacitor and the capacitor charges again. The process of charging and discharging the capacitor occurs during a predetermined time period and the number of times the capacitor switches during the time period represents the resistance of the memory element.

Abstract: A pair of self-biased differential amplifiers having a non-symmetrical topology are combined to provide a self-biased differential amplifier having a symmetrical topology. Each of the combined differential amplifiers includes a pair of transistors coupled to each other as a current mirror. The current mirror transistors are coupled in series with a respective one of a pair of differential input transistors. A current source transistor is coupled to the differential input transistors, and it is self-biased by one of the current mirror transistors.

Abstract: A circuit for reducing a mismatch between a reference path to which a reference voltage is applied and an intensity path to which an intensity voltage is applied from an active pixel sensor comprises a first and a second pair of switches and a processing circuit. The first pair of switches couple an intensity input node to which the intensity voltage is applied to a first output node and couple a reference input node to which the reference voltage is applied to a second output node during a first operating period. The second pair of switches couple the intensity input node to the second output node and couple the reference input node to the first output node during a second operating period. A polarity reversing circuit is included in the processing circuit for coupling the first and second output nodes to the processing circuit with one polarity during the first operating period and in a reverse polarity during the second operating period.

Abstract: A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a switching point modulation circuit coupled to input logic and configured to modulate the periodic output signal from the input logic such that the periodic output signal is centered about a known voltage signal, such as a switching point voltage signal.

Abstract: A system and methods optimize the operation of sensing circuitry. In one embodiment, the output of a sensing circuit is stored in a register and processed through logic gates to determine whether the sensing output contains a predetermined string of logic ones or zeroes. If a string of ones is detected, the logic gates activate a counter to increase the operating clock frequency for the sensing circuit. If a string of zeroes is detected, the logic gates activate the counter to decrease the frequency.

Abstract: A phase splitter using digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.

Abstract: A phase detector is comprised of two cross-coupled gates which are capable of phase discrimination down to a level of approximately 10 picoseconds. An arbiter circuit, responsive to the cross-coupled gates, generates mutually exclusive UP and DOWN pulse signals. The UP and DOWN pulse signals may be filtered and used to control the delay line of an all digital delay locked or phase locked loop.

Abstract: Electrically conductive polymer composite materials comprised of: a) an effective amount of substantially crystalline graphitic carbon nanofibers comprised of graphite sheets that are substantially parallel to the longitudinal axis of the nanofiber, preferably wherein said grip sheets form a multifaceted tubular structure; and b) a polymeric component.

Abstract: Novel catalysts comprised of graphitic nanostructures. The graphitic nanostructure catalysts are suitable for catalyzing reactions such as oxidation, hydrogenation, oxidative-hydrogenation, and dehydrogenation.

Abstract: The input buffer circuit includes an input stage providing a switching point voltage based on a predetermined switching point set between a first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input buffer circuit further includes an output stage. The output stage is coupled to the input stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.