Abstract: The invention relates to a field-effect transistor and a method for its manufacturing having at least one layer, said layer comprising a III-V compound semiconductor, wherein the compound semiconductor comprises at least one element from the chemical group III being selected from any of gallium, aluminum, indium and/or boron and wherein the compound semiconductor comprises at least one element from the chemical group V being selected from nitrogen, phosphorous and/or arsenic, wherein the compound semiconductor comprises at least nitrogen, wherein the field-effect transistor comprises at least any of a source electrode and/or a drain electrode, said source electrode and/or drain electrode comprising at least one doped region extending from the surface into the at least one layer, wherein the depth of penetration of said doped region is selected from approximately 10 nm to approximately 200 nm.

Abstract: The invention relates to a field-effect transistor and a method for its manufacturing having at least one layer, said layer comprising a III-V compound semiconductor, wherein the compound semiconductor comprises at least one element from the chemical group III being selected from any of gallium, aluminium, indium and/or boron and wherein the compound semiconductor comprises at least one element from the chemical group V being selected from nitrogen, phosphorous and/or arsenic, wherein the compound semiconductor comprises at least nitrogen, wherein the field-effect transistor comprises at least any of a source electrode and/or a drain electrode, said source electrode and/or drain electrode comprising at least one doped region extending from the surface into the at least one layer, wherein the depth of penetration of said doped region is selected from approximately 10 nm to approximately 200 nm.

Abstract: A semiconductor structure includes a barrier layer, a spacer structure, and a channel layer. The barrier layer includes a group III nitride. The spacer structure includes first and second aluminum nitride layers and an intermediate layer. The intermediate layer includes a group III nitride and is between the first and second aluminum nitride layers. The intermediate layer has a first free charge carrier density at an interface with the second aluminum nitride layer. The spacer structure is between the barrier layer and the channel layer. The channel layer includes a group III nitride and has a second free charge carrier density at an interface with the first aluminum nitride layer of the spacer structure. The first aluminum nitride layer, the intermediate layer, and the second aluminum nitride layer have layer thicknesses so the first free charge carrier density is less than 10% of the second free charge carrier density.

Abstract: A semiconductor structure includes a barrier layer, a spacer structure, and a channel layer. The barrier layer includes a group III nitride. The spacer structure includes first and second aluminum nitride layers and an intermediate layer. The intermediate layer includes a group III nitride and is between the first and second aluminum nitride layers. The intermediate layer has a first free charge carrier density at an interface with the second aluminum nitride layer. The spacer structure is between the barrier layer and the channel layer. The channel layer includes a group III nitride and has a second free charge carrier density at an interface with the first aluminum nitride layer of the spacer structure. The first aluminum nitride layer, the intermediate layer, and the second aluminum nitride layer have layer thicknesses so the first free charge carrier density is less than 10% of the second free charge carrier density.