Abstract: A clock recovery mechanism for an ATM receiver recovers a service (source) clock transmitted over an ATM network. The mechanism includes an input for receiving an SRTS from the ATM network, a local SRTS generator for locally generating an SRTS, a comparator for comparing a received SRTS and a locally generated SRTS and a recovered service clock generator responsive to an output of the comparator for generating the recovered service clock and for controlling the local SRTS generator. The locally generated SRTS is compared directly with the received SRTS. The local SRTS is generated using the same method as used to generate the transmitted SRTS, that is using the network clock fnx and a locally generated clock, at frequency fs. The difference between the locally generated SRTS and the received SRTS can be expressed directly in a number of fnx pulse clocks to be added or removed to the generated fs clock. Thus a service clock can be recovered at a receiver location using SRTSs by means of a digital technique.

Abstract: In order to reduce memory requirements in a chip for demodulating digital video broadcast signals, symbol data values stored for a channel equalisation process have their scattered pilots removed, to achieve a 9% reduction in memory space required. This is achieved by providing a write pointer and a read pointer, the write pointer being arranged to exclude carriers carrying scattered pilots, and the read pointer being arranged to read the stored symbol data, but to add nominal data values at positions of excluded scattered pilots.

Abstract: A clock recovery mechanism for an ATM receiver recovers a service (source) clock transmitted over an ATM network. The mechanism includes an input for receiving an SRTS from the ATM network, a local SRTS generator for locally generating an SRTS, a comparator for comparing a received SRTS and a locally generated SRTS and a recovered service clock generator responsive to an output of the comparator for generating the recovered service clock and for controlling the local SRTS generator. The locally generated SRTS is compared directly with the received SRTS. The local SRTS is generated using the same method as used to generate the transmitted SRTS, that is using the network clock fnx and a locally generated clock, at frequency fs. The difference between the locally generated SRTS and the received SRTS can be expressed directly in a number of fnx pulse clocks to be added or removed to the generated fs clock. Thus a service clock can be recovered at a receiver location using SRTSs by means of a digital technique.

Abstract: A demodulator suitable for implementation in a single chip for demodulating digital video broadcast signals comprising data modulated on a multiplicity of spaced carrier frequencies, wherein an input broadcast signal is converted to a frequency sufficiently low to enable analog digital conversion of the signal, the demodulator comprising analog to digital conversion means (20) for converting the broadcast signal to a series of digital samples, real to complex conversion means (22) for converting each digital sample to a complex number value, Fourier transform means (24) for analyzing the complex number values to provide a series of signal values for each carrier frequency, frequency control means (9, 38), comprising means responsive to the output of said Fourier Transform means for producing a signal for controlling the frequency of the signal formed by said complex number values, and signal processing means for receiving the signal values and providing an output for decoding, the signal processing means incl

Abstract: Apparatus for demodulating digital video broadcast signals with an improved automatic frequency control comprises data modulated on a multiplicity of spaced carrier frequencies, including: analog to digital conversion device for providing a series of digital samples of the broadcast signal, Fourier Transform for analysing the samples to provide a series of data signal values for each carrier frequency signal processing devices for processing the series of data signal values including the phase-error-correcting, and automatic frequency control device for controlling the frequency of the signals input to the Fourier Transform Processor, wherein the automatic frequency control device includes coarse frequency control unit for controlling the frequency in terms of increments of the carrier spacing frequency, and fine frequency control unit for controlling the frequency for values less than a single carrier spacing frequency interval, wherein the coarse frequency unit includes recursive of filtering for assessing

Abstract: In order to correct for common phase error in demodulated digital video broadcast signals which comprise data modulated on a multiplicity of spaced carrier frequencies, a demodulator includes analog to digital conversion means (20) for providing a series of digital samples of the broadcast signal, real to complex conversion means (22) for converting each digital sample to a complex number value, Fourier Transform means (24) for analysing the complex number values to provide a series of data signal values in complex number format for each carrier frequency, and signal processing means for processing the series of data signal values including phase error correcting means (30), the phase error correcting means including means for converting the data signal values from a complex number format to a phase angle format, means for determining a common phase error by assessing the phase of continual pilot signals in the broadcast signals and determining the variation in phase of the continual pilot signals between c

Abstract: Adaptive clock recovery enables the clock of a CBR service to be recovered, this service being emulated from an ATM transmitter, is provided at an ATM receiver. The fill level of a first buffer receiving a stream of cells is used to provide coarse control of the rate of output of a stream of cells from the first buffer. The fill level of a further, fine, buffer receiving said stream of cells from the first buffer is monitored for determining a clock frequency, corresponding to the service clock frequency, for outputting cells from the fine buffer. The first buffer fill level control provides low pass cell jitter filtering by selectively supplying a first or a second clock frequency for outputting cells from the first buffer. The fine filter fill level control employs a phase locked loop responsive to the current fill level to set a clock frequency for reading out said fine buffer at the service clock frequency.