Patents by Inventor R. Holt
R. Holt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990535Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.Type: GrantFiled: October 27, 2021Date of Patent: May 21, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Alexander M. Derrickson, Haiting Wang, Judson R. Holt, Vibhor Jain, Richard F. Taylor, III
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Publication number: 20240162345Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a metal field plate contact and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a shallow trench isolation structure within the semiconductor substrate; and a contact extending from the gate structure and into the shallow trench isolation structure.Type: ApplicationFiled: November 10, 2022Publication date: May 16, 2024Inventors: Shesh M. PANDEY, Rajendran KRISHNASAMY, Judson R. HOLT, Chung Foong TAN
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Patent number: 11977258Abstract: Disclosed are a structure with a substrate-embedded waveguide and a method of forming the structure. The waveguide includes cladding material lining a trench in a substrate, a core in the trench on the cladding material, and at least one cavity within the core. Each cavity extends from one end of the core toward the opposite end and contains a low refractive index material or is under vacuum so the waveguide is an arrow waveguide. An insulator layer is on the substrate and extends laterally over the waveguide and a semiconductor layer is on the insulator layer. Additionally, depending upon the embodiment, an additional waveguide can be aligned above the substrate-embedded waveguide either on the isolation region or on a waveguide extender that extends at least partially through the isolation region and the insulator layer to the waveguide.Type: GrantFiled: December 29, 2022Date of Patent: May 7, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Laura J. Silverstein, Steven M. Shank, Judson R. Holt, Yusheng Bian
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Patent number: 11969985Abstract: A method of using a sterilization wrap system including a permeable material having barrier properties and having a first surface and a second opposing surface, the exterior panel being substantially opaque or having a first level of translucence, and an interior panel including a permeable material having barrier properties and having a first surface and a second opposing surface, the interior panel having a level of translucence that is higher than the translucence of the exterior panel, the panels being joined together over at least a portion of their surfaces. Also disclosed is inspection of the sterilization wrap system for exterior panel breaches by looking for light passing through a panel facing the viewer.Type: GrantFiled: April 25, 2023Date of Patent: April 30, 2024Assignee: O&M Halyard, Inc.Inventors: Jeffrey James Farmer, Kelly L. Holt, Ronald K. Anderson, Melissa R. Gaynor, Corinna Schwarz
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Publication number: 20240136400Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.Type: ApplicationFiled: January 5, 2024Publication date: April 25, 2024Inventors: Alexander Derrickson, Vibhor Jain, Judson R. Holt, Jagar Singh, Mankyu Yang
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Patent number: 11954597Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using embedded function with a deep network. One of the methods includes receiving an input comprising a plurality of features, wherein each of the features is of a different feature type; processing each of the features using a respective embedding function to generate one or more numeric values, wherein each of the embedding functions operates independently of each other embedding function, and wherein each of the embedding functions is used for features of a respective feature type; processing the numeric values using a deep network to generate a first alternative representation of the input, wherein the deep network is a machine learning model composed of a plurality of levels of non-linear operations; and processing the first alternative representation of the input using a logistic regression classifier to predict a label for the input.Type: GrantFiled: October 24, 2022Date of Patent: April 9, 2024Assignee: Google LLCInventors: Gregory S. Corrado, Kai Chen, Jeffrey A. Dean, Gary R. Holt, Julian P. Grady, Sharat Chikkerur, David W. Sculley, II
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Patent number: 11949004Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and a gate structure comprising a gate oxide and a gate control in a same channel region as the extrinsic base region.Type: GrantFiled: November 23, 2021Date of Patent: April 2, 2024Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Judson R. Holt, Vibhor Jain, Alexander M. Derrickson
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Publication number: 20240105503Abstract: A transistor is provided. The transistor includes a substrate, a gate structure, a semiconductor structure, and a dielectric component. The gate structure is over the substrate and the semiconductor structure is adjacent to the gate structure. The semiconductor structure has a first side facing the gate structure and a second side laterally opposite the first side. The dielectric component is in the substrate. The dielectric component has a first portion adjacent to the second side of the semiconductor structure and a second portion under the first portion, wherein the second portion extends under the gate structure.Type: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Inventors: SHESH MANI PANDEY, RAJENDRAN KRISHNASAMY, JUDSON R. HOLT
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Patent number: 11942534Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with thermal conductor and methods of manufacture. The structure includes: a base formed within a semiconductor substrate; a thermal conductive material under the base and extending to an underlying semiconductor material; an emitter on a first side of the base; and a collector on a second side of the base.Type: GrantFiled: May 16, 2022Date of Patent: March 26, 2024Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Hong Yu, Judson R. Holt, Vibhor Jain
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Patent number: 11935923Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.Type: GrantFiled: November 12, 2021Date of Patent: March 19, 2024Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Alexander Derrickson, Vibhor Jain, Judson R. Holt, Jagar Singh, Mankyu Yang
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Patent number: 11916109Abstract: Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.Type: GrantFiled: May 26, 2022Date of Patent: February 27, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Peter Baars, Alexander M. Derrickson, Ketankumar Harishbhai Tailor, Zhixing Zhao, Judson R. Holt
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Patent number: 11907685Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.Type: GrantFiled: November 8, 2019Date of Patent: February 20, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Judson R. Holt, Julien Frougier, Ryan W. Sporer, George R. Mulfinger, Daniel Jaeger
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Patent number: 11888031Abstract: In a disclosed semiconductor structure, a lateral bipolar junction transistor (BJT) has a base positioned laterally between a collector and an emitter. The base includes a semiconductor fin with a first portion that extends from a substrate through an isolation layer, a second portion on the first portion, and a third portion on the second portion. The collector and emitter are on the isolation layer and positioned laterally immediately adjacent to opposing sidewalls of the second portion of the semiconductor fin. In some embodiments, the BJT is a standard BJT where the semiconductor fin (i.e., the base), the collector, and the emitter are made of the same semiconductor material. In other embodiments, the BJT is a heterojunction bipolar transistor (HBT) where a section of the semiconductor fin (i.e., the base) is made of a different semiconductor material for improved performance. Also disclosed is a method of forming the structure.Type: GrantFiled: November 30, 2021Date of Patent: January 30, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Hong Yu, Judson R. Holt, Zhenyu Hu
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Patent number: 11888050Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with inner and outer spacers, and related methods. A lateral bipolar transistor structure may have an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A first base layer is on the insulator and adjacent the E/C layer. The first base layer has a second doping type opposite the first doping type. A second base layer is on the first base layer and having the second doping type. A dopant concentration of the second base layer is greater than a dopant concentration of the first base layer. An inner spacer is on the E/C layer and adjacent the second base layer. An outer spacer is on the E/C layer and adjacent the inner spacer.Type: GrantFiled: December 2, 2021Date of Patent: January 30, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: John L. Lemon, Alexander M. Derrickson, Haiting Wang, Judson R. Holt
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Patent number: 11881395Abstract: Embodiments of the disclosure provide a lateral bipolar transistor on a semiconductor fin and methods to form the same. A bipolar transistor structure according to the disclosure may include a doped semiconductor layer coupled to a base contact. A first semiconductor fin on the doped semiconductor layer may have a first doping type. An emitter/collector (E/C) material may be on a sidewall of an upper portion of the first semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.Type: GrantFiled: December 17, 2021Date of Patent: January 23, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Judson R. Holt, Hong Yu, Alexander M. Derrickson
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Patent number: 11881523Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a subcollector under a buried insulator layer; a collector above the subcollector; a base within the buried insulator layer; an emitter above the base; and contacts to the subcollector, the base and the emitter.Type: GrantFiled: May 10, 2022Date of Patent: January 23, 2024Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Shesh Mani Pandey, Vibhor Jain, Judson R. Holt
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Publication number: 20240021713Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.Type: ApplicationFiled: September 27, 2023Publication date: January 18, 2024Inventors: Haiting Wang, Alexander Derrickson, Jagar Singh, Vibhor Jain, Andreas Knorr, Alexander Martin, Judson R. Holt, Zhenyu Hu
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Patent number: 11869958Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a collector in a semiconductor substrate; a subcollector in the semiconductor substrate; an intrinsic base over the subcollector; an extrinsic base adjacent to the intrinsic base; an emitter over the intrinsic base; and an isolation structure between the extrinsic base and the emitter and which overlaps the subcollector.Type: GrantFiled: May 16, 2022Date of Patent: January 9, 2024Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Judson R. Holt, Shesh Mani Pandey, Vibhor Jain
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Publication number: 20240006517Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted âTâ shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.Type: ApplicationFiled: September 19, 2023Publication date: January 4, 2024Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
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Patent number: 11862717Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a superlattice layer and methods to form the same. The bipolar transistor structure may have a semiconductor layer of a first single crystal semiconductor material over an insulator layer. The semiconductor layer includes an intrinsic base region having a first doping type. An emitter/collector (E/C) region may be adjacent the intrinsic base region and may have a second doping type opposite the first doping type. A superlattice layer is on the E/C region of the semiconductor layer. A raised E/C terminal, including a single crystal semiconductor material, is on the superlattice layer. The superlattice layer separates the E/C region from the raised E/C terminal.Type: GrantFiled: November 24, 2021Date of Patent: January 2, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Vibhor Jain, John J. Pekarik, Alvin J. Joseph, Alexander M. Derrickson, Judson R. Holt