Abstract: A modular array processor architecture (10) comprising a plurality of interconnected parallel processing node (11)s that each comprise a control processor (12), an arithmetic processor (13) having an input port (22) for receiving data from an external source that is to be processed, a node memory (14) that also comprises a portion of a distributed global memory, and a network interface (15) coupled between the control processor (12), the arithmetic processor (13), and the node memory (14). Data and control buses (17, 18) are coupled between the arithmetic processors (13) and network interfaces (14) of each of the processing nodes (11). Respective network interfaces (15) link each of the arithmetic processors (13), node memories (14) and control processors (12) together to provide for communication throughout the architecture (10) and permit each node to communicate with the node memories (14) of all other processing nodes (11).

Abstract: A signal processor comprising a split pipelined parallel processor which processes data signals from external signal sources and provides signal processing functions utilizing a plurality of data formats. The signal processor comprises an external interface unit having a serial control port and a plurality of bidirectional parallel ports. The interface unit transfers control and data signals between the signal processor and external devices. The parallel ports are configurable as individual parallel ports or coupled pairs which form a port having the combined data path of the two coupled ports. An arithmetic element controller comprising a microprogram memory and a control program memory is coupled to the interface unit which loads applications programs into the control program memory and executes the programs. The arithmetic element controller controls the processing of control and data signals in the signal processor.

Abstract: A single instruction stream multiple data steam data flow signal processor and method for implementing macro data flow control, in which a plurality of data processors have contentionless access to global memory data. Data processing tasks for the data processors, such as primitive executions together with graph scheduling processes, are developed asynchronously and in parallel from a command program and a macro data flow control graph.