Patents by Inventor Rémi Teyssier

Rémi Teyssier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Marking long latency instruction as branch in pending instruction table and handle as mis-predicted branch upon interrupting event to return to checkpointed state
    Patent number: 9513925
    Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: December 6, 2016
    Assignee: ARM Limited
    Inventors: Nicolas Chaussade, Florent Begon, Melanie Emanuelle Lucie Teyssier, Remi Teyssier, Jocelyn Francois Orion Jaubert
  • Dynamic instruction splitting
    Patent number: 8782378
    Abstract: A data processing apparatus and method are provided. The data processing apparatus is configured to perform data processing operations in response to data processing instructions including a multiple operation instruction, in response to which multiple data processing operations are performed. The data processing apparatus comprises two or more data processing units configured to perform the data processing operations and an instruction arbitration unit configured to perform sub-division of a multiple operation instruction into a plurality of sub-instructions and to perform allocation of the plurality of sub-instructions amongst the two or more data processing units, wherein each sub-instruction is arranged to cause one of the two or more data processing units to perform at least one data processing operation of the multiple data processing operations.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: July 15, 2014
    Assignee: ARM Limited
    Inventors: Nicolas Chaussade, Rémi Teyssier
  • DATA PROCESSING APPARATUS AND METHOD USING CHECKPOINTING
    Publication number: 20140019734
    Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency.
    Type: Application
    Filed: September 19, 2013
    Publication date: January 16, 2014
    Applicant: ARM LIMITED
    Inventors: Nicolas CHAUSSADE, Florent BEGON, Melanie Emanuelle Lucie TEYSSIER, Remi TEYSSIER, Jocelyn Francois Orion JAUBERT
  • Checkpointing long latency instruction as fake branch in branch prediction mechanism
    Patent number: 8578139
    Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: November 5, 2013
    Assignee: ARM Limited
    Inventors: Nicolas Chaussade, Florent Begon, Mélanie Emanuelle Lucie Teyssier, Rémi Teyssier, Jocelyn Francois Orion Jaubert
  • Control of clock gating
    Patent number: 8352794
    Abstract: Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: January 8, 2013
    Assignee: ARM Limited
    Inventors: Remi Teyssier, Florent Begon, Jocelyn Francois Orion Jaubert, Cédric Denis Robert Airaud
  • Dynamic instruction splitting
    Publication number: 20120066481
    Abstract: A data processing apparatus and method are provided. The data processing apparatus is configured to perform data processing operations in response to data processing instructions including a multiple operation instruction, in response to which multiple data processing operations are performed. The data processing apparatus comprises two or more data processing units configured to perform the data processing operations and an instruction arbitration unit configured to perform sub-division of a multiple operation instruction into a plurality of sub-instructions and to perform allocation of the plurality of sub-instructions amongst the two or more data processing units, wherein each sub-instruction is arranged to cause one of the two or more data processing units to perform at least one data processing operation of the multiple data processing operations.
    Type: Application
    Filed: September 14, 2010
    Publication date: March 15, 2012
    Applicant: ARM LIMITED
    Inventors: Nicolas Chaussade, Rémi Teyssier
  • Data processing apparatus and method using checkpointing
    Publication number: 20120036340
    Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency.
    Type: Application
    Filed: August 5, 2010
    Publication date: February 9, 2012
    Applicant: ARM Limited
    Inventors: Nicolas Chaussade, Florent Begon, Mélanie Emanuelle Lucie Teyssier, Rémi Teyssier, Jocelyn Francois Orion Jaubert
  • Control of clock gating
    Publication number: 20100162063
    Abstract: Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal.
    Type: Application
    Filed: November 19, 2009
    Publication date: June 24, 2010
    Applicant: ARM LIMITED
    Inventors: Remi Teyssier, Florent Begon, Jocelyn Francois Orion Jaubert, Cédric Denis Robert Airaud