Patents by Inventor Rémy GASSILLOUD
Rémy GASSILLOUD has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12120889Abstract: A method for manufacturing a microelectronic device including resistive memory points, a first portion of the memory points forming a physical unclonable function, the memory points of the first portion forming a PUF zone, a second portion of the memory points providing a memory function, the memory points of the second forming a memory zone, the method including providing a support including a first electrode layer and an active oxide resistive memory layer; etching the active oxide resistive memory layer in the PUF zone; etching the active oxide resistive memory layer in the memory zone, the etching in the memory zone producing a dispersion of roughness of the oxide layer less than the dispersion of roughness produced by the etching in the PUF zone; depositing a second electrode layer; etching the second electrode layer, the active oxide layer and the first electrode layer to define the memory points.Type: GrantFiled: November 23, 2021Date of Patent: October 15, 2024Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVESInventors: Christelle Charpin-Nicolle, Florian Pebay-Peyroula, Rémy Gassilloud, Nicolas Guillaume
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Publication number: 20240237561Abstract: A resistive memory device including at least one first electrode based on a first metal and a second electrode based on a second metal, and a memory element in the form of a metal filament based on a third metal and inserted between the first and second electrodes, the memory element having a filament cross-section strictly smaller than the electrode cross-sections, wherein the third metal has a chemical composition, different from those of the first and second metals giving it an etching speed greater than those of the first and second metals, preferably such that the selectivity at the etching is greater than or equal to 3:1, vis-á-vis the first and second metals. A method for manufacturing such a device is also disclosed.Type: ApplicationFiled: October 25, 2023Publication date: July 11, 2024Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Christelle CHARPIN-NICOLLE, Serge BLONKOWSKI, Rémy GASSILLOUD, Thomas MAGIS
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Publication number: 20240203731Abstract: A method including the following successive steps: a) forming, on a surface of a support substrate, a first layer made of a material selected from among a lamellar dichalcogenide or a lamellar chalcogenide including a stack of sheets; b) forming, by physical vapor deposition on the side of said surface of the support substrate, a second layer made of a first III-N semiconductor material coating the first layer; and c) carrying out a thermo-chemical treatment of the first layer resulting, in the first layer, in a conversion of van der Waals bonds between the sheets of the first layer into covalent bonds.Type: ApplicationFiled: December 13, 2023Publication date: June 20, 2024Applicant: Commissariat à I'Énergie Atomique et aux Énergies AlternativesInventors: Rémy Gassilloud, Julien Patouillard, Bérangére Hyot, Amélie Dussaigne, Stéphane Cadot, Matthew Charles, François Martin, Nicolas Gauthier, Christine Raynaud
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Publication number: 20240194485Abstract: A method for manufacturing a field effect transistor including a silicon-germanium active layer and a gate oxide layer disposed on the active layer, the method including providing a stack including a substrate and a silicon-germanium first layer disposed on the substrate; forming the gate oxide layer on the stack; subjecting the stack to laser annealing so as to melt a region of the stack, the region including at least one part of the first layer, and recrystallising the molten region of the stack to obtain the silicon-germanium active layer in contact with the gate oxide layer, the active layer having a germanium concentration gradient.Type: ApplicationFiled: December 13, 2023Publication date: June 13, 2024Inventors: Pablo ACOSTA ALBA, Claire FENOUILLET-BERANGER, Rémy GASSILLOUD, Sébastien KERDILES, Shay REBOH
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Publication number: 20240138273Abstract: A resistive memory device including at least one first electrode based on a first metal and a second electrode based on a second metal, and a memory element in the form of a metal filament based on a third metal and inserted between the first and second electrodes, the memory element having a filament cross-section strictly smaller than the electrode cross-sections, wherein the third metal has a chemical composition, different from those of the first and second metals giving it an etching speed greater than those of the first and second metals, preferably such that the selectivity at the etching is greater than or equal to 3:1, vis-á-vis the first and second metals. A method for manufacturing such a device is also disclosed.Type: ApplicationFiled: October 24, 2023Publication date: April 25, 2024Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Christelle CHARPIN-NICOLLE, Serge BLONKOWSKI, Rémy GASSILLOUD, Thomas MAGIS
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Publication number: 20230183857Abstract: A method is for depositing a thin tungsten and/or molybdenum sulfide film on a substrate chemically, under vacuum.Type: ApplicationFiled: December 14, 2022Publication date: June 15, 2023Applicant: Commissariat à l'Energie Atomique et aux Energies AlternativesInventors: Rémy GASSILLOUD, Stéphane CADOT
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Publication number: 20230060860Abstract: A method for producing a resistive memory cell from a stack of layers having a metal-oxide layer interleaved between first and second electrodes includes forming, within one from among the first and second electrodes, an interlayer material-based electrode interlayer having a selectivity to etching greater than or equal to 2:1 relative to materials of the electrodes. During an etching of the stack, overetching is performed configured to laterally consume, in a horizontal direction, the interlayer material such that the electrode interlayer has a lateral recess greater than or equal to 10 nm.Type: ApplicationFiled: August 31, 2022Publication date: March 2, 2023Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Christelle CHARPIN-NICOLLE, Mathieu BERNARD, Rémy GASSILLOUD, Thomas MAGIS
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Patent number: 11377735Abstract: A device for depositing at least one radical chalcogenide thin film on an element to be treated including an intake area and a diffusion area receiving the element to be treated, the intake area and the diffusion area extending along a longitudinal axis, a radical hydrogen source connected to the intake area, pumping means, means for injecting a reagent reacting with the radical hydrogen to form H2S, and means for supplying a precursor to the diffusion area. The injection means inject the reagent into a central area of the intake area in the longitudinal direction within the radical hydrogen flow. The pumping means are controlled so as to operate during the reagent injection, and generate a flow of H2S along the element to be treated in order to activate said element so as to absorb the precursor.Type: GrantFiled: October 31, 2017Date of Patent: July 5, 2022Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Remy Gassilloud
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Publication number: 20220165792Abstract: A method for manufacturing a microelectronic device including resistive memory points, a first portion of the memory points forming a physical unclonable function, the memory points of the first portion forming a PUF zone, a second portion of the memory points providing a memory function, the memory points of the second forming a memory zone, the method including providing a support including a first electrode layer and an active oxide resistive memory layer; etching the active oxide resistive memory layer in the PUF zone; etching the active oxide resistive memory layer in the memory zone, the etching in the memory zone producing a dispersion of roughness of the oxide layer less than the dispersion of roughness produced by the etching in the PUF zone; depositing a second electrode layer; etching the second electrode layer, the active oxide layer and the first electrode layer to define the memory points.Type: ApplicationFiled: November 23, 2021Publication date: May 26, 2022Inventors: Christelle CHARPIN-NICOLLE, Florian PEBAY-PEYROULA, Rémy GASSILLOUD, Nicolas GUILLAUME
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Patent number: 11329224Abstract: An OxRAM oxide based resistive random access memory cell includes a first electrode; a layer M1Oss of a sub-stoichiometric oxide of a first metal; a layer M2N of a nitride of a second metal M2; a layer M3M4O of a ternary alloy of a third metal M3, a fourth metal M4 and oxygen O, or M3M4NO of a quaternary alloy of the third metal M3, the fourth metal M4, nitrogen N and oxygen O and a second electrode. The standard free enthalpy of formation of the ternary alloy M3M4O, noted ?Gf,T0 (M3M4O), or of the quaternary alloy M3M4NO, noted ?Gf,T0 (M3M4NO), is strictly less than the standard free enthalpy of formation of the sub-stoichiometric oxide M1Oss of the first metal M1, noted ?Gf,T0 (M1Oss), itself less than or equal to the standard free enthalpy of formation of any ternary oxynitride M2NO of the second metal M2, noted ?Gf,T0 (M2NO): ?Gf,T0(M3M4O)<?Gf,T0(M1Oss)??Gf,T0(M2NO) or ?Gf,T0(M3M4NO)<?Gf,T0(M1Oss)??Gf,T0(M2NO).Type: GrantFiled: December 12, 2019Date of Patent: May 10, 2022Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Rémy Gassilloud, Mathieu Bernard, Christelle Charpin-Nicolle
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Patent number: 11031554Abstract: The present invention relates to a method for producing a via through a base layer of a microelectronic device, the method including formation of a hole leading to at least one first face of the base layer and filling the hole by at least one first filling material. The method also includes at least partially removing the at least one first filling material over a depth from the first face of the base layer, the depth being strictly less than a thickness dimension of the hole, so as to produce a hollow portion. Further, method includes a second step of at least partially filling the hollow portion by at least one second filling material.Type: GrantFiled: December 20, 2018Date of Patent: June 8, 2021Assignee: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Christelle Charpin-Nicolle, Remy Gassilloud, Alain Persico
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Publication number: 20210010133Abstract: A method to manufacture a film made of vanadium disulphide by chemical vapor deposition on a previously heated substrate, includes successive procedures implemented in a vacuum reactor: injection of at least one organometallic molecule of vanadium, where the vanadium has a valence of less than or equal to 4; drainage of the reactor; injection of at least one sulphur molecule including at least one free thiol group, or forming a reaction intermediate comprising at least one free thiol group; injection of a reducing gas.Type: ApplicationFiled: June 26, 2020Publication date: January 14, 2021Inventors: Rémy GASSILLOUD, Stéphane CADOT, Mathias FRACCAROLI
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Publication number: 20200194671Abstract: An OxRAM oxide based resistive random access memory cell includes a first electrode; a layer M1Oss of a sub-stoichiometric oxide of a first metal; a layer M2N of a nitride of a second metal M2; a layer M3M4O of a ternary alloy of a third metal M3, a fourth metal M4 and oxygen O, or M3M4NO of a quaternary alloy of the third metal M3, the fourth metal M4, nitrogen N and oxygen O and a second electrode.Type: ApplicationFiled: December 12, 2019Publication date: June 18, 2020Inventors: Rémy GASSILLOUD, Mathieu BERNARD, Christelle CHARPIN-NICOLLE
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Publication number: 20190256975Abstract: The invention relates to a device for depositing at least one radical chalcogenide thin film on an element to be treated including an intake area (4) and a diffusion area (6) receiving the element (P) to be treated, the intake area (4) and the diffusion area (6) extending along a longitudinal axis (Z), a radical hydrogen source (8) connected to the intake area (4), pumping means (19), means for injecting a reagent reacting with the radical hydrogen to form H2S, and means for supplying a precursor to the diffusion area. The injection means inject the reagent into a central area of the intake area (4) in the longitudinal direction within the radical hydrogen flow. The pumping means (19) are controlled so as to operate during the reagent injection, and generate a flow of H2S along the element to be treated (P) in order to activate said element so as to absorb the precursor.Type: ApplicationFiled: October 31, 2017Publication date: August 22, 2019Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Remy GASSILLOUD
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Publication number: 20190252611Abstract: The present invention relates to a method for producing a via through a base layer of a microelectronic device, the method including formation of a hole leading to at least one first face of the base layer and filling the hole by at least one first filling material. The method also includes at least partially removing the at least one first filling material over a depth from the first face of the base layer, the depth being strictly less than a thickness dimension of the hole, so as to produce a hollow portion. Further, method includes a second step of at least partially filling the hollow portion by at least one second filling material.Type: ApplicationFiled: December 20, 2018Publication date: August 15, 2019Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Christelle CHARPIN-NICOLLE, Remy Gassilloud, Alain Persico
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Patent number: 9768379Abstract: A resistive non-volatile memory cell including a Metal-Insulation-Metal stack including two electrodes and a multilayer of insulation, placed between the two electrodes, including a thin layer of oxide allowing for a resistive transition and an oxygen vacancy reservoir layer is provided. The stack includes from bottom to top: the bottom electrode including a metal layer, the insulation including a layer of stoichiometric metal oxide and a layer of substoichiometric metal oxide forming the oxygen vacancy reservoir layer, and the top electrode including a layer of metal oxide and a metal layer, such that the oxygen vacancy reservoir layer is inserted between two metal oxide stoichiometric layers.Type: GrantFiled: January 6, 2016Date of Patent: September 19, 2017Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Remy Gassilloud, Mathieu Bernard
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Publication number: 20160197271Abstract: A resistive non-volatile memory cell including a Metal-Insulation-Metal stack including two electrodes and a multilayer of insulation, placed between the two electrodes, including a thin layer of oxide allowing for a resistive transition and an oxygen vacancy reservoir layer is provided. The stack includes from bottom to top: the bottom electrode including a metal layer, the insulation including a layer of stoichiometric metal oxide and a layer of substoichiometric metal oxide forming the oxygen vacancy reservoir layer, and the top electrode including a layer of metal oxide and a metal layer, such that the oxygen vacancy reservoir layer is inserted between two metal oxide stoichiometric layers.Type: ApplicationFiled: January 6, 2016Publication date: July 7, 2016Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Remy GASSILLOUD, Mathieu BERNARD
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Patent number: 8609522Abstract: A process for producing a conducting electrode on a substrate, including: depositing a layer made of a dielectric; depositing a protective layer made of the nitride of a metal on the dielectric layer; depositing a functionalization layer made of a material including a chemical species, such that the free enthalpy of formation of the nitride of the species is less, in absolute value, than the free enthalpy of formation of the nitride of the metal of the protective layer over the temperature range between 0° C. and 1200° C.; and annealing the assembly including the protective layer and the funtionalization layer so that the species diffuse from the functionalization layer into the protective layer and the nitrogen atoms migrate from the protective layer into the functionalization layer.Type: GrantFiled: March 11, 2011Date of Patent: December 17, 2013Assignee: Commissariat à l'énergie atomique et aux ènergies alternativesInventors: Remy Gassilloud, François Martin
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Publication number: 20130075832Abstract: A process for producing a conducting electrode on a substrate, including: depositing a layer made of a dielectric; depositing a protective layer made of the nitride of a metal on the dielectric layer; depositing a functionalization layer made of a material including a chemical species, such that the free enthalpy of formation of the nitride of the species is less, in absolute value, than the free enthalpy of formation of the nitride of the metal of the protective layer over the temperature range between 0° C. and 1200° C.; and annealing the assembly including the protective layer and the funtionalization layer so that the species diffuse from the functionalization layer into the protective layer and the nitrogen atoms migrate from the protective layer into the functionalization layer.Type: ApplicationFiled: March 11, 2011Publication date: March 28, 2013Applicant: Commissariat a l' energie atomique et aux energies alternativesInventors: Remy Gassilloud, François Martin