Patents by Inventor R. P. G. Karunasiri

R. P. G. Karunasiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6156654
    Abstract: Methods are disclosed for forming ultra-thin (.about.300-.ANG.), uniform and stoichiometric C54-titanium silicide with a Ti film thickness of 200-300 .ANG. using pulsed laser salicidation. The invention achieves this by preferably step-scanning from die to die, across the wafer using laser pulses with an optical fluence (laser energy) ranging from 0.1 to 0.2 J/cm.sup.2 for approximately 23 nanoseconds per pulse. The source of radiation can be a XeCl or KrF excimer laser, or one in which the laser's wavelength is chosen such that the laser energy is absorbed the most by the refractory metal, i.e. titanium (Ti), cobalt (Co) or nickel (Ni). The laser beam size is typically die-size or can be fine tuned to 1 to 100 .mu.m and can be optimized to reduce the intensity variation across the laser spot diameter. At each position between 1 to 100 pulses can be emitted on the wafer. Localized heating is possible with the ability to establish the ambient temperature at or below 200.degree. C.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: December 5, 2000
    Assignees: Chartered Semiconductor Manufacturing Ltd., National University of Singapore
    Inventors: Chaw Sing Ho, Yuan Ping Lee, Chan Lap, Yong Feng Lu, R. P.G. Karunasiri
  • Patent number: 6010954
    Abstract: A method to form a "mushroom shaped" gate structure 18 22 44A 70 that increases the top gate silicide contact area and improves the salicide process, especially TiSi.sub.2 salicide. The novel upper gate extensions 44A increase the top gate surface area so that the silicide gate contacts 70 will have a low resistivity. The invention includes forming a gate stack 18 22 26 comprised of a gate oxide layer 18, a center gate portion 22 and a hard mask 26. Next, we form a first insulating layer 40 over the gate stack 22 26 18. The hard mask 26 and a first thickness of the first insulating layer 40 are removed to expose sidewalls of the center gate portion 22. A second conductive layer 44 is formed over the first insulating layer 46 and the center gate portion 22. The second conductive layer 44 is etched to form critical rounded upper gate extensions 44A on the sidewalls of the center gate portion 22. Lower rectangular sidewall spacers 52 are formed on the sidewalls of the center gate portion 22.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: January 4, 2000
    Assignees: Chartered Semiconductor Manufacturing, Ltd., National University of Singapore
    Inventors: Chaw Sing Ho, R. P. G. Karunasiri, Soo Jin Chua, Kin Leong Pey, Kong Hean Lee