Patents by Inventor R. Peter Smith

R. Peter Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of forming group III-nitride semiconductor devices including implanting ions directly into source and drain regions and annealing to activate the implanted ions
    Patent number: 9711633
    Abstract: Methods of forming a semiconductor device include forming a dielectric layer on a Group III-nitride semiconductor layer, selectively removing portions of the dielectric layer over spaced apart source and drain regions of the semiconductor layer, implanting ions having a first conductivity type directly into the source and drain regions of the semiconductor layer, annealing the semiconductor layer and the dielectric layer to activate the implanted ions, and forming metal contacts on the source and drain regions of the semiconductor layer.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: July 18, 2017
    Assignee: Cree, Inc.
    Inventors: Scott T. Sheppard, R. Peter Smith, Yifeng Wu, Sten Heikman, Matthew Jacob-Mitos
  • Methods of fabricating transistors including self-aligned gate electrodes and source/drain regions
    Patent number: 8105889
    Abstract: Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: January 31, 2012
    Assignee: Cree, Inc.
    Inventors: R. Peter Smith, Scott T. Sheppard
  • SEMICONDUCTOR DEVICES INCLUDING SHALLOW IMPLANTED REGIONS AND METHODS OF FORMING THE SAME
    Publication number: 20110057232
    Abstract: Methods of forming a semiconductor device include forming a dielectric layer on a Group III-nitride semiconductor layer, selectively removing portions of the dielectric layer over spaced apart source and drain regions of the semiconductor layer, implanting ions having a first conductivity type directly into the source and drain regions of the semiconductor layer, annealing the semiconductor layer and the dielectric layer to activate the implanted ions, and forming metal contacts on the source and drain regions of the semiconductor layer.
    Type: Application
    Filed: May 9, 2008
    Publication date: March 10, 2011
    Inventors: Scott T. Sheppard, R. Peter Smith, Yifeng Wu, Sten Heikman, Matthew Jacob-Mitos
  • METHODS OF FABRICATING TRANSISTORS INCLUDING SELF-ALIGNED GATE ELECTRODES AND SOURCE/DRAIN REGIONS
    Publication number: 20110018040
    Abstract: Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.
    Type: Application
    Filed: July 27, 2009
    Publication date: January 27, 2011
    Inventors: R. Peter Smith, Scott T. Sheppard
  • Dual polarized, heat spreading rectenna
    Patent number: 5907305
    Abstract: An aperture coupled patch splits energy from two different polarization components to different locations to spread heat. In addition, there is no physical electrical connection between the slot, patch and circuitry. The circuitry is located under a ground plane which shields against harmonic radiation back to the RF source.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: May 25, 1999
    Assignee: California Institute of Technology
    Inventors: Larry W. Epp, Abdur R. Khan, R. Peter Smith, Hugh K. Smith