Abstract: The invention reduces test development time for a circuit by determining the longest delay through each circuit element input and output pin. The delays are determined by calculating a delay value metric for each input pin and output pin and by assigning a delay value metric to the respective pin. Branch depth and branch width values are calculated for each input and output pin, and branch width and branch depth values are assigned to the respective pin. A least slack path is determined from the delay metric values. A fault model defines criteria for detection of faults at each circuit element pin using a test vector and associates a delay with each detected fault. The fault model enables detection of more than a single fault by a test vector.

Abstract: The invention reduces test development time for a circuit by determining the longest delay through each circuit element input and output pin. The delays are determined by calculating a delay value metric for each input pin and output pin and by assigning a delay value metric to the respective pin. Branch depth and branch width values are calculated for each input and output pin, and branch width and branch depth values are assigned to the respective pin. A least slack path is determined from the delay metric values. A fault model defines criteria for detection of faults at each circuit element pin using a test vector and associates a delay with each detected fault. The fault model enables detection of more than a single fault by a test vector.