Abstract: P-type layers of a GaN based light-emitting device are optimized for formation of Ohmic contact with metal. In a first embodiment, a p-type GaN transition layer with a resistivity greater than or equal to about 7 ? cm is formed between a p-type conductivity layer and a metal contact. In a second embodiment, the p-type transition layer is any III-V semiconductor. In a third embodiment, the p-type transition layer is a superlattice. In a fourth embodiment, a single p-type layer of varying composition and varying concentration of dopant is formed.

Abstract: P-type layers of a GaN based light-emitting device are optimized for formation of Ohmic contact with metal. In a first embodiment, a p-type GaN transition layer with a resistivity greater than or equal to about 7 ?cm is formed between a p-type conductivity layer and a metal contact. In a second embodiment, the p-type transition layer is any III-V semiconductor. In a third embodiment, the p-type transition layer is a superlattice. In a fourth embodiment, a single p-type layer of varying composition and varying concentration of dopant is formed.

Abstract: P-type layers of a GaN based light-emitting device are optimized for formation of Ohmic contact with metal. In a first embodiment, a p-type GaN transition layer with a resistivity greater than or equal to about 7 &OHgr;cm is formed between a p-type conductivity layer and a metal contact. In a second embodiment, the p-type transition layer is any III-V semiconductor. In a third embodiment, the p-type transition layer is a superlattice. In a fourth embodiment, a single p-type layer of varying composition and varying concentration of dopant is formed.

Abstract: P-type layers of a GaN based light-emitting device are optimized for formation of Ohmic contact with metal. In a first embodiment, a p-type GaN transition layer with a resistivity greater than or equal to about 7 &OHgr;cm is formed between a p-type conductivity layer and a metal contact. In a second embodiment, the p-type transition layer is any III-V semiconductor. In a third embodiment, the p-type transition layer is a superlattice. In a fourth embodiment, a single p-type layer of varying composition and varying concentration of dopant is formed.

Abstract: A smoothing structure containing indium is formed between the substrate and the active region of a III-nitride light emitting device to improve the surface characteristics of the device layers. In some embodiments, the smoothing structure is a single layer, separated from the active region by a spacer layer which typically does not contain indium. The smoothing layer contains a composition of indium lower than the active region, and is typically deposited at a higher temperature than the active region. The spacer layer is typically deposited while reducing the temperature in the reactor from the smoothing layer deposition temperature to the active region deposition temperature. In other embodiments, a graded smoothing region is used to improve the surface characteristics. The smoothing region may have a graded composition, graded dopant concentration, or both.

Abstract: An epitaxial material grown laterally in a trench allows for the fabrication of a trench-based semiconductor material that is substantially low in dislocation density. Initiating the growth from a sidewall of a trench minimizes the density of dislocations present in the lattice growth template, which minimizes the dislocation density in the regrown material. Also, by allowing the regrowth to fill and overflow the trench, the low dislocation density material can cover the entire surface of the substrate upon which the low dislocation density material is grown. Furthermore, with successive iterations of the trench growth procedure, higher quality material can be obtained. Devices that require a stable, high quality epitaxial material can then be fabricated from the low dislocation density material.

Abstract: A smoothing structure containing indium is formed between the substrate and the active region of a III-nitride light emitting device to improve the surface characteristics of the device layers. In some embodiments, the smoothing structure is a single layer, separated from the active region by a spacer layer which typically does not contain indium. The smoothing layer contains a composition of indium lower than the active region, and is typically deposited at a higher temperature than the active region. The spacer layer is typically deposited while reducing the temperature in the reactor from the smoothing layer deposition temperature to the active region deposition temperature. In other embodiments, a graded smoothing region is used to improve the surface characteristics. The smoothing region may have a graded composition, graded dopant concentration, or both.

Abstract: A smoothing structure containing indium is formed between the substrate and the active region of a III-nitride light emitting device to improve the surface characteristics of the device layers. In some embodiments, the smoothing structure is a single layer, separated from the active region by a spacer layer which typically does not contain indium. The smoothing layer contains a composition of indium lower than the active region, and is typically deposited at a higher temperature than the active region. The spacer layer is typically deposited while reducing the temperature in the reactor from the smoothing layer deposition temperature to the active region deposition temperature. In other embodiments, a graded smoothing region is used to improve the surface characteristics. The smoothing region may have a graded composition, graded dopant concentration, or both.

Abstract: A smoothing structure containing indium is formed between the substrate and the active region of a III-nitride light emitting device to improve the surface characteristics of the device layers. In some embodiments, the smoothing structure is a single layer, separated from the active region by a spacer layer which typically does not contain indium. The smoothing layer contains a composition of indium lower than the active region, and is typically deposited at a higher temperature than the active region. The spacer layer is typically deposited while reducing the temperature in the reactor from the smoothing layer deposition temperature to the active region deposition temperature. In other embodiments, a graded smoothing region is used to improve the surface characteristics. The smoothing region may have a graded composition, graded dopant concentration, or both.

Abstract: A semiconductor device is provided having n-type device layers of III-V nitride having donor dopants such as germanium (Ge), silicon (Si), tin (Sn), and/or oxygen (O) and/or p-type device layers of III-V nitride having acceptor dopants such as magnesium (Mg), beryllium (Be), zinc (Zn), and/or cadmium (Cd), either simultaneously or in a doping superlattice, to engineer strain, improve conductivity, and provide longer wavelength light emission.

Abstract: Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.

Abstract: Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.

Abstract: P-type layers of a GaN based light-emitting device are optimized for formation of Ohmic contact with metal. In a first embodiment, a p-type GaN transition layer with a resistivity greater than or equal to about 7 &OHgr;cm is formed between a p-type conductivity layer and a metal contact. In a second embodiment, the p-type transition layer is any III-V semiconductor. In a third embodiment, the p-type transition layer is a superlattice. In a fourth embodiment, a single p-type layer of varying composition and varying concentration of dopant is formed.

Abstract: Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.

Abstract: Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.

Abstract: In the present invention, an interfacial layer is added to a light-emitting diode or laser diode structure to perform the role of strain engineering and impurity gettering. A layer of GaN or AlxInyGa1−x−yN (0≦x≦1, 0≦y≦1) doped with Mg, Zn, Cd can be used for this layer. Alternatively, when using AlxInyGa1−x−yN (x>0), the layer may be undoped. The interfacial layer is deposited directly on top of the buffer layer prior to the growth of the n-type (GaN:Si) layer and the remainder of the device structure. The thickness of the interface layer varies from 0.01-10.0 &mgr;m.

Abstract: In the present invention, an interfacial layer is added to a light-emitting diode or laser diode structure to perform the role of strain engineering and impurity gettering. A layer of GaN or AlxInyGal1-x-yN (0≦x≦1, 0≦y≦1) doped with Mg, Zn, Cd can be used for this layer. Alternatively, when using AlxInyGa1-x-yN (x>0), the layer may be undoped. The interfacial layer is deposited directly on top of the buffer layer prior to the growth of the n-type (GaN:Si) layer and the remainder of the device structure. The thickness of the interfacial layer varies from 0.01-10.0 &mgr;m.

Abstract: A buried reflector 50 in an epitaxial lateral growth layer forms a part of a light emitting device and allows for the fabrication of a semiconductor material that is substantially low in dislocation density. The laterally grown material is low in dislocation defect density where it is grown over the buried reflector making it suitable for high quality optical light emitting devices, and the embedded reflector eliminates the need for developing an additional reflector.