Patents by Inventor R. Stanley Williams

R. Stanley Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10497440
    Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, and a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections. Each junction comprises a resistive memory element, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: December 3, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Miao Hu, John Paul Strachan, Zhiyong Li, R. Stanley Williams
  • Publication number: 20190363251
    Abstract: An electrically actuated switch comprises a first electrode, a second electrode, and an active region disposed therebetween. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). Methods of operating the switch are also provided.
    Type: Application
    Filed: August 5, 2019
    Publication date: November 28, 2019
    Inventor: R. Stanley Williams
  • Patent number: 10374155
    Abstract: An electrically actuated switch comprises a first electrode, a second electrode, and an active region disposed therebetween. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). Methods of operating the switch are also provided.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 6, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: R. Stanley Williams
  • Publication number: 20190066780
    Abstract: Examples herein relate to linear transformation accelerators. An example linear transformation accelerator may include a crossbar array programmed to calculate a linear transformation. The crossbar array has a plurality of words lines, a plurality of bit lines, and a memory cell coupled between each unique combination of one word line and one bit line, where the memory cells are programmed according to a linear transformation matrix. The plurality of word lines are to receive an input vector, and the plurality of bit lines are to output an output vector representing a linear transformation of the input vector.
    Type: Application
    Filed: February 19, 2016
    Publication date: February 28, 2019
    Inventors: Miao Hu, John Paul Strachan, Zhiyong Li, R. Stanley Williams
  • Publication number: 20180373675
    Abstract: A technique includes providing a first set of values to a memristor crossbar array and using the memristor crossbar array to perform a Fourier transformation. Using the memristor crossbar array to perform the Fourier transform includes using the array to apply a Discrete Fourier Transform (DFT) to the first set of values to provide a second set of values.
    Type: Application
    Filed: January 28, 2016
    Publication date: December 27, 2018
    Applicant: Hewlett Packard Enterprise Development LP
    Inventors: John Paul Strachan, Miao Hu, R. Stanley Williams, Zhiyong Li
  • Patent number: 10162263
    Abstract: An integrated circuit may include a substrate with a plurality of transistors formed in the substrate. The plurality of transistors may be coupled to a first metal layer formed over the plurality of transistors. A plurality of high dielectric nanometer capacitors may be formed of memristor switch material between the first metal layer and a second metal layer formed over the plurality of high dielectric capacitors. The plurality of high dielectric capacitors may operate as memory storage cells in dynamic logic.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: December 25, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Zhiyong Li, Jianhua Yang, R. Stanley Williams
  • Patent number: 10153729
    Abstract: In some examples, a device includes a nano-scale oscillator that exhibits chaotic oscillation responsive to a control input to the nano-scale oscillator, where the control input including a tunable input parameter.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: December 11, 2018
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Suhas Kumar, John Paul Strachan, Gary Gibson, R. Stanley Williams
  • Patent number: 10147762
    Abstract: Protective elements are provided for non-volatile memory cells in crossbar arrays in which each memristor is situated at a crosspoint of the array. Each memristor is provided with a protective element. The protective element includes a layer of a first oxide that upon heating converts to a second oxide having a higher resistivity than the first oxide.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: December 4, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Minxian Max Zhang, Jianhua Yang, R. Stanley Williams
  • Publication number: 20180336947
    Abstract: A memristor includes a bottom electrode, a top electrode, and an active region disposed therebetween. The active region has an electrically conducting filament in an electrically insulating medium, extending between the bottom electrode and the top electrode. The memristor further includes a temperature gradient element for controlling switching.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Gary Gibson, R. Stanley Williams
  • Publication number: 20180314927
    Abstract: According to an example, a hybrid synaptic architecture based neural network may be implemented by determining, from input data, information that is to be recognized, mined, and/or synthesized by a plurality of analog neural cores. Further, the hybrid synaptic architecture based neural network may be implemented by determining, based on the information, selected ones of the plurality of analog neural cores that are to be actuated to identify a data subset of the input data to generate, based on the analysis of the data subset, results of the recognition, mining, and/or synthesizing of the information.
    Type: Application
    Filed: October 30, 2015
    Publication date: November 1, 2018
    Inventors: Naveen Muralimanohar, John Paul Strachan, Rajeev Balasubramonian, R. Stanley Williams
  • Publication number: 20180301189
    Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, and a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections. Each junction comprises a resistive memory element, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
    Type: Application
    Filed: August 7, 2015
    Publication date: October 18, 2018
    Inventors: Miao Hu, John Paul Strachan, Zhiyong Li, R. Stanley Williams
  • Patent number: 10056142
    Abstract: A device for generating a representative logic indicator of grouped memristors is described. The device includes a memristor array. The memristor array includes a number of first memristors having a first set of logic indicators and a number of second memristors having a second set of logic indicators. The second set of logic indicators is different than the first set of logic indicators. Each first memristor is grouped with a corresponding second memristor during a memory read operation to generate a representative logic indicator.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: August 21, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Jianhua Yang, Zhiyong Li, R. Stanley Williams
  • Patent number: 10049738
    Abstract: A memristor includes a bottom electrode, a top electrode, and an active region disposed therebetween. The active region has an electrically conducting filament in an electrically insulating medium, extending between the bottom electrode and the top electrode. The memristor further includes a temperature gradient element for controlling switching.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: August 14, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gary Gibson, R. Stanley Williams
  • Patent number: 10008666
    Abstract: Examples of the present disclosure include non-volatile resistive memory cells and methods of forming the same. An example of a non-volatile resistive memory cell includes a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure on a first electrode, where the first portion comprises at least one memristive material across a width of the vertically-extending structure. The non-volatile resistive memory cell also includes a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: June 26, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Hans S Cho, Janice H Nickel, R. Stanley Williams, Jaesung Roh, Jinwon Park, Choi Hyejung, Moonsig Joo, Jiwon Moon, Changgoo Lee, Yongsun Sohn, Jeongtae Kim
  • Publication number: 20180075904
    Abstract: A memristive crossbar array is described. The crossbar array includes a number of row lines and a number of column lines intersecting the row lines to form a number of cross points. A number of memristor cells are coupled between the row lines and the column lines at the cross points. A memristor cell includes a memristive memory element to store information and multiple selectors electrically coupled to the memristive memory element. The multiple selectors are to provide access to the memristive memory element.
    Type: Application
    Filed: April 27, 2015
    Publication date: March 15, 2018
    Inventors: Ning Ge, Jianhua Yang, Zhiyong Li, R. Stanley Williams
  • Patent number: 9905757
    Abstract: A nonlinear memristor device with a three-layer selector includes a memristor in electrical series with a three-layer selector. The memristor comprises at least one electrically conducting layer and at least one electrically insulating layer. The three-layer selector comprises a three-layer structure selected from the group consisting of XN—XO—XN; XN—YO—ZN; XN—YO—XN; XO—XN—XO; XO—YN—XO; XO—YN—ZO; XO—YO—XO; XO—YO—ZO; XN—YN—ZN; and XN—YN—XN, X represents a compound-forming metal different from Y and Z.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: February 27, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Byungjoon Choi, Jianhua Yang, R. Stanley Williams, Gary Gibson, Warren Jackson
  • Publication number: 20180017870
    Abstract: An integrated circuit may include a substrate with a plurality of transistors formed in the substrate. The plurality of transistors may be coupled to a first metal layer formed over the plurality of transistors. A plurality of high dielectric nanometer capacitors may be formed of memristor switch material between the first metal layer and a second metal layer formed over the plurality of high dielectric capacitors. The plurality of high dielectric capacitors may operate as memory storage cells in dynamic logic.
    Type: Application
    Filed: April 27, 2015
    Publication date: January 18, 2018
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning GE, Zhiyong LI, Jianhua Yang, R. Stanley Williams
  • Publication number: 20170372782
    Abstract: A memristor includes a bottom electrode, a top electrode, and an active region disposed therebetween. The active region has an electrically conducting filament in an electrically insulating medium, extending between the bottom electrode and the top electrode. The memristor further includes a temperature gradient element for controlling switching.
    Type: Application
    Filed: December 17, 2014
    Publication date: December 28, 2017
    Inventors: Gary Gibson, R. Stanley Williams
  • Patent number: 9846565
    Abstract: Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: December 19, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Matthew D. Pickett, R. Stanley Williams, Gilberto M. Ribeiro
  • Patent number: 9847126
    Abstract: A method of increasing a read margin in a memory cell may include sensing an input current created from the application of a read voltage across a memristive device, squaring the input current, and comparing the squared input current to a reference current. A memristive device may include a memristor and a sense amplifier communicatively coupled to the memristor wherein a sensed input current created from the application of a reference voltage across a memristor is squared and wherein the sense amplifier compares the squared input current to a reference current.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: December 19, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, R. Stanley Williams