Abstract: A packet switching device having a central shared memory and a number of medium access controllers each coupled to a communications medium to exchange data packets, and a controller coupled to each medium access controller via a data path to exchange data packets with the media access controller. The controller has a number of data path controllers each connected to each medium access controller to exchange a corresponding portion of the data packets with the medium access controller. The data path controllers each have a number of buffers to hold the portion of the data packets exchanged with the corresponding medium access controller. Each data path controller has a selector that selects the buffer from which to exchange the portion of the data packets with the central shared memory and control logic that controls the selector to concurrently select the buffer corresponding to the same medium access controller.

Abstract: A packet switching device having a central shared memory and a number of medium access controllers each coupled to a communications medium to exchange data packets therewith, and a controller coupled to each medium access controller via a data path to exchange data packets with the media access controller. The controller has a number of data path controllers each connected to each medium access controller via a separate and like portion of the data path to exchange a corresponding portion of the data packets with the medium access controller. The data path controllers each have a number of buffers each connected to one of the medium access controllers to which the data path controller is connected, to hold the portion of the data packets exchanged with the corresponding medium access controller.

Abstract: A packet switching device having a central shared memory and a number of medium access controllers each coupled to a communications medium to exchange data packets therewith, and a controller coupled to each medium access controller via a data path to exchange data packets with the media access controller. The controller has a number of data path controllers each connected to each medium access controller via a separate and like portion of the data path to exchange a corresponding portion of the data packets with the medium access controller. The data path controllers each have a number of buffers each connected to one of the medium access controllers to which the data path controller is connected, to hold the portion of the data packets exchanged with the corresponding medium access controller.

Abstract: An apparatus and a method are provided for smoothing out high frequency information in an interlaced computer generated display. A computer generated RGB signal is converted into a YUV signal, which is separated into its Y, U, and V components. The Y component is convolved by averaging a current scan line with a line above and a line below the current scan line so that black lines are lightened and white lines are darkened, thus avoiding flicker. Since convolution is only performed on the Y part of the YUV signal, only two line buffers, each having a width equal to the number of bits in the Y component only, are required.

Abstract: A method for transferring data between a host computer and peripheral storage including the steps of: (a) receiving data from the host; (b) determining if an escape command is present in the data; (c) writing the data to the a peripheral storage medium if a escape command is not present in the data; and (d) performing as least one command relative to the peripheral storage if a escape command is present in the data. Also disclosed is a method for controlling a disk drive unit including the steps of: (a) determining on a host computer a current action to be performed with a disk drive unit; (b) formatting a track of a disk engaged with a disk drive unit based upon output data provided by the host computer if the current action is a formatting action; (c) writing a sector on the disk based upon the output data provided by the host computer if the current action is a writing action; and (d) reading a sector of the disk and transferring input information to the host computer if the action is a reading action.

Abstract: A self-identifying scheme which permits a variety of integrated circuit semiconductor memory modules to inform a host processor as to each individual memory accessing speed or accessing time. Pre-encoded circuits within each memory module generate a coded signal when that module is selected by the host processor. The coded signal identifies the type of memory accessed, permitting the host processor to transfer information at a rate determined by the memory accessed.

Abstract: A power manager within a portable laptop computer provides power and clocking control to various units within the computer in order to conserve battery power. Transistor switches controlled by the power manager control the distribution of power and/or clock signals to the various units within the computer. The power manager includes a software routine for continually monitoring the various units and when these units are either not needed and/or not currently in use, power and/or clock signals are removed from a given unit.