Abstract: A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal.

Abstract: A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal.

Abstract: A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal.

Abstract: A filter includes at least a pin diode, an inductive element, and a varactor diode coupled as a resonant circuit. The filter injects data dependent jitter into a digital data signal with a given data rate for testing a transceiver.

Abstract: A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal.

Abstract: An apparatus to receive a response signal sent from a device under test. The apparatus includes pin electronics to identify a response signal contained in a composite signal. The composite signal is a composite, or sum, of the response signal and a test signal. The pin electronics has a driver to send the test signal to the device under test, and a receiver to receive the composite signal and to separate the response signal from the composite signal.

Abstract: An apparatus to receive a response signal sent from a device under test. The apparatus includes pin electronics to identify a response signal contained in a composite signal. The composite signal is a composite, or sum, of the response signal and a test signal. The pin electronics has a driver to send the test signal to the device under test, and a receiver to receive the composite signal and to separate the response signal from the composite signal.

Abstract: A method is described that decompresses at least a section of a first test pattern within a first decompression engine while simultaneously decompressing at least a section of a second test pattern within a second decompression engine. The first test pattern is to be applied to a first device under test (DUT) connection. The second test pattern is to be applied to a second DUT connection.

Abstract: A method and apparatus for generating timing markers in an automatic electrical test system. Timing parameters are synchronized by an external period start signal corresponding to a centrally generated external period and an internal period start signal generated locally for each input/output pin. The timing parameters comprise T1 counter and vernier values, T2 counter and vernier values, and period-minus-T1 counter and period vernier values.

Abstract: A phase shift vernier for providing an output signal with continuously variable delay based on an input phase delay is disclosed. The apparatus comprises delay value means, a ring oscillator, a multiplexer, a DAC, and a signal combiner. The delay value means is adapted for receiving an input phase delay value, indicating the amount of delay for an output signal. The ring oscillator is adapted for circulating an oscillating signal through multiple differential stages to generate multiple quadrature signals. The oscillating signal has a predetermined frequency and each of the differential stages is connected in series. Each of the stages delays its inputs by a predetermined amount to generate its differential outputs from each stage. The multiplexor is coupled to the ring oscillator and to the delay value means to receive the quadrature signals from the ring oscillator.

Abstract: A high speed voltage comparator circuit is disclosed which accepts a wide range of input potentials CBO1 and compares them with four potential levels CRH, CRL, CRIH, and CRIL. Each comparator includes input transistors Q103 and Q104, one of which is connected to the reference potential and the other is connected to the unknown potential. The emitters of the input transistors Q103 and Q104 are connected together through a resistor R105, and each emitter is connected to a current source, Q105 and Q107 respectively. A third current source Q106 is coupled to diodes D101 and D102 which are connected to the emitters of transistors Q103 and Q104 respectively. The difference between the reference potential and the unknown potential will forward bias one of the diodes and reverse bias the other. The resulting difference in emitter current between the input transistors Q103 and Q104 is detected by an output stage to indicate the relative magnitudes of the reference potential and the unknown potential.

Abstract: An automatic test system for parallel loading of data into pin registers 100 associated with pins of a device being tested includes data bus 130 for transmitting data; an address bus 120 for transmitting addresses; a set of pin registers 100, each having a unique address and each coupled to receive information from the data bus 130; a participate register 150 coupled to data bus 130 and to each of registers 100 for enabling selected ones of registers 100 to receive data from the data bus at the same time; an address decoder 110, 180 connected to the address bus 120, to each of registers 100, and to the participate register 150, for enabling one of the pin registers 100 or the participate register 150 to receive data from the data bus, the data for the participate register 150 comprising the addresses of each of the selected ones of pin registers 100 which are to receive data from the data bus in parallel.

Abstract: A tri-state driver circuit 10 for selectively driving a node of a device under test by applying and switching between two reference voltages, and for selectively operating at a high impedance output state. Two current sources 16 and 18 provide a bridge current that flows through a diode bridge 20 to establish, at nodes A and B, voltages that equal two reference voltages, DRH and DRL. The diode bridge includes resistors R11 and R16 across which the bridge current is switched to accommodate small voltage swings, and also includes clamp diodes CR3-6 to accommodate large voltage swings. A current switch 22 controls the direction of the bridge current and the selection of which of the two reference voltages appears at node A. A current sink 36, 38, and 40 monitors the average voltage of the diode bridge and adjusts it to equal the average of the two reference voltages.