Abstract: A method, apparatus, and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.

Abstract: A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.

Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for balancing hardware trace collection between hardware trace facilities. A first hardware trace facility is included within a first processor. The first processor includes multiple processing units coupled together utilizing a first system bus. A second hardware trace facility is included within a second processor. The second processor includes multiple processing units coupled together utilizing a second system bus. Bus traffic is transmitted between the first and second system busses such that the first and second processors receive data transmitted on both busses. A type of trace data is specified to be captured from the first and second system busses.

Abstract: A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.

Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol.