Patents by Inventor Raashina Humayun
Raashina Humayun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240084443Abstract: A showerhead includes a plurality of plenums and a plurality of through holes positioned in the plurality of plenums. The plenums are stacked in a sequential order in an axial direction perpendicular to a semiconductor substrate. The plenums extend radially fully across the semiconductor substrate. The plenums are disjoint from each other and are configured to respectively supply a first metal precursor, a second metal precursor, and a reactant via the respective plenums without intermixing the first metal precursor, the second metal precursor, and the reactant in the plenums. The through holes of the respective plenums are arranged in a radial direction, which is perpendicular to the axial direction, in the same sequential order as the sequential order of the plenums. The through holes of the plenums open along a flat surface at a bottom of the showerhead. The flat surface extends radially fully across the bottom of the showerhead.Type: ApplicationFiled: November 27, 2023Publication date: March 14, 2024Inventors: Ilanit FISHER, Raashina Humayun, Michal Danek, Patrick Van Cleemput, Shruti Thombare
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Patent number: 11901227Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.Type: GrantFiled: October 8, 2021Date of Patent: February 13, 2024Assignee: Lam Research CorporationInventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Patent number: 11827976Abstract: A method includes arranging a substrate in a processing chamber, and exposing the substrate to a gas mixture including a first metal precursor gas and a second metal precursor gas to deposit a first metal precursor and a second metal precursor onto the substrate at the same time. The method further includes purging the processing chamber, supplying a reactant common to both the first metal precursor and the second metal precursor to form a layer of an alloy on the substrate, and purging the processing chamber.Type: GrantFiled: December 6, 2018Date of Patent: November 28, 2023Assignee: LAM RESEARCH CORPORATIONInventors: Ilanit Fisher, Raashina Humayun, Michal Danek, Patrick Van Cleemput, Shruti Thombare
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Patent number: 11670516Abstract: Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.Type: GrantFiled: August 19, 2019Date of Patent: June 6, 2023Assignee: Lam Research CorporationInventors: Karthik S. Colinjivadi, Samantha SiamHwa Tan, Shih-Ked Lee, George Matamis, Yongsik Yu, Yang Pan, Patrick Van Cleemput, Akhil Singhal, Juwen Gao, Raashina Humayun
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Publication number: 20230041794Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.Type: ApplicationFiled: June 28, 2022Publication date: February 9, 2023Inventors: Anand CHANDRASHEKAR, Esther JENG, Raashina Humayun, Michal DANEK, Juwen GAO, Deqi WANG
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Patent number: 11410883Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.Type: GrantFiled: March 6, 2019Date of Patent: August 9, 2022Assignee: Novellus Systems, Inc.Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Publication number: 20220223471Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: ApplicationFiled: January 31, 2022Publication date: July 14, 2022Inventors: Shruti Vivek THOMBARE, Raashina HUMAYUN, Michal DANEK, Chiukin Steven LAI, Joshua COLLINS, Hanna BAMNOLKER, Griffin John KENNEDY, Gorun BUTAIL, Patrick A. van Cleemput
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Patent number: 11348795Abstract: Disclosed are methods of depositing a transition metal such as tungsten on a semiconductor substrate. The method includes providing a gas mixture of diborane with a balance of hydrogen, where the hydrogen serves to stabilize the diborane in the gas mixture. The method further includes delivering the gas mixture to the semiconductor substrate to form a boron layer, where the boron layer serves as a reducing agent layer to convert a metal-containing precursor to metal, such as a tungsten-containing precursor to tungsten. In some implementations, the semiconductor substrate includes a vertical structure, such as a three-dimensional vertical NAND structure, with horizontal features or wordlines having openings in sidewalls of the vertical structure, where the boron layer may be conformally deposited in the horizontal features of the vertical structure.Type: GrantFiled: August 10, 2018Date of Patent: May 31, 2022Assignee: Lam Research CorporationInventors: Lawrence Schloss, Raashina Humayun, Sanjay Gopinath, Juwen Gao, Michal Danek, Kaihan Abidi Ashtiani
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Publication number: 20220102208Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.Type: ApplicationFiled: October 8, 2021Publication date: March 31, 2022Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Publication number: 20210327754Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).Type: ApplicationFiled: June 25, 2021Publication date: October 21, 2021Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Publication number: 20210242032Abstract: Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.Type: ApplicationFiled: August 19, 2019Publication date: August 5, 2021Inventors: Karthik S. COLINJIVADI, Samantha SiamHwa TAN, Shih-Ked LEE, George MATAMIS, Yongsik YU, Yang PAN, Patrick VAN CLEEMPUT, Akhil SINGHAL, Juwen GAO, Raashina HUMAYUN
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Patent number: 11075115Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).Type: GrantFiled: September 6, 2018Date of Patent: July 27, 2021Assignee: Novellus Systems, Inc.Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Patent number: 10916434Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.Type: GrantFiled: February 10, 2020Date of Patent: February 9, 2021Assignee: Lam Research CorporationInventors: Deqi Wang, Anand Chandrashekar, Raashina Humayun, Michal Danek
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Publication number: 20200407842Abstract: A method includes arranging a substrate in a processing chamber, and exposing the substrate to a gas mixture including a first metal precursor gas and a second metal precursor gas to deposit a first metal precursor and a second metal precursor onto the substrate at the same time. The method further includes purging the processing chamber, supplying a reactant common to both the first metal precursor and the second metal precursor to form a layer of an alloy on the substrate, and purging the processing chamber.Type: ApplicationFiled: December 6, 2018Publication date: December 31, 2020Inventors: Ilanit FISHER, Raashina HUMAYUN, Michal DANEK, Patrick VAN CLEEMPUT, Shruti THOMBARE
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Publication number: 20200365456Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: ApplicationFiled: July 27, 2020Publication date: November 19, 2020Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick van Cleemput
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Patent number: 10777453Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: GrantFiled: November 6, 2019Date of Patent: September 15, 2020Assignee: Lam Research CorporationInventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
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Patent number: 10731250Abstract: In some embodiments, deposition processes for ruthenium (Ru) feature fill include deposition of a thin, protective Ru film under reducing conditions, followed by a Ru fill step under oxidizing conditions. The presence of protective Ru films formed under oxygen-free conditions or with an oxygen-removing operation can enable Ru fill without oxidation of an underlying adhesion layer or metal feature.Type: GrantFiled: June 4, 2018Date of Patent: August 4, 2020Assignee: Lam Research CorporationInventors: Do Young Kim, Jeong-Seok Na, Chiukin Steven Lai, Raashina Humayun, Michal Danek
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Publication number: 20200211853Abstract: Disclosed are methods of depositing a transition metal such as tungsten on a semiconductor substrate. The method includes providing a gas mixture of diborane with a balance of hydrogen, where the hydrogen serves to stabilize the diborane in the gas mixture. The method further includes delivering the gas mixture to the semiconductor substrate to form a boron layer, where the boron layer serves as a reducing agent layer to convert a metal-containing precursor to metal, such as a tungsten-containing precursor to tungsten. In some implementations, the semiconductor substrate includes a vertical structure, such as a three-dimensional vertical NAND structure, with horizontal features or wordlines having openings in sidewalls of the vertical structure, where the boron layer may be conformally deposited in the horizontal features of the vertical structure.Type: ApplicationFiled: August 10, 2018Publication date: July 2, 2020Inventors: Lawrence Schloss, Raashina Humayun, Sanjay Gopinath, Juwen Gao, Michal Danek, Kaihan Abidi Ashtiani
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Publication number: 20200185225Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.Type: ApplicationFiled: February 10, 2020Publication date: June 11, 2020Inventors: Deqi Wang, Anand Chandrashekar, Raashina Humayun, Michal Danek
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Publication number: 20200185273Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang