Abstract: Embodiments of the invention provide methods and apparatuses to provide concurrent execution of multiple instruction threads for independent control of two or more subsystems of a communication device. One embodiment includes a memory containing a plurality of instruction threads. Each of the plurality of instruction threads contains a timing specification and a corresponding timing reference. An execution unit is coupled to the memory. The execution unit concurrently executes each of the plurality of instruction threads in accordance with the timing specification and the corresponding timing reference of each instruction thread.

Abstract: According to an embodiment of the invention, a method and apparatus are described for data bit sequences. According to an embodiment of the invention, a header is inserted in a data burst. One or more high priority messages of a first type are optionally inserted in the data burst starting after the header. One or more messages of a second type are optionally inserted into the data burst starting at an end of the data burst. One or more low priority messages of the first type are optionally inserted in the data.