Abstract: A method for handling a control transfer instruction couple includes fetching a plurality of instructions. The plurality of instructions include a control transfer instruction couple (or CTI couple), which includes a first branch instruction and a second branch instruction, leading instructions that precede the first branch instruction, trailing instructions that follow the second branch instruction, and buffered instructions that follow the trailing instructions. The method further includes decoding the CTI couple, forwarding the leading instructions and the first branch instruction for processing, freezing the trailing instructions and the delay slot to obtain frozen instructions, buffering the buffered instructions fetched after the freezing, and initiating an instruction refetch cycle dependent on a prediction of an execution of the first branch instruction.

Abstract: A method for handling instructions that use non-windowed registers in an out-of-order microprocessor with windowed registers is provided. When an instruction with a non-windowed destination register is detected, the computed result of the instruction is stored in a temporary storage register instead of the non-windowed register designated as the instruction's destination. When the instruction is ready for retirement, the result is transferred from the temporary storage register into the non-windowed register designated as the instruction's destination. When another instruction's source register is a non-windowed register, the microprocessor determines whether the instruction should use data from the designated non-windowed register or from a temporary storage register, to prevent the other instruction from using incorrect data.

Abstract: A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.

Abstract: A method for handling a conditional move instruction using a two read port per issue slot register file, where the conditional move instruction references a first register, a second register, and a third register is provided. The method involves decoding a conditional move instruction, invoking at least two helper instructions dependent on the decoding, evaluating a register condition of the first register using a first helper instruction, and updating the third register with the contents of either the second register third register dependent on the evaluating using a second helper instruction.

Abstract: A method for determining a reifetch address of a branch instruction in a set of instructions involves decoding the set of instructions, forwarding the set of instructions along with a value of a branch counter, updating the branch counter based on the set of instructions, and predicting a result of executing the branch instruction in the set of instructions. If mispredicted, a source address of the branch instruction is calculated. The calculating involves shifting the value of the branch counter dependent on a shift value to generate a shifted value of the branch counter, and adding a working copy of the program counter or next program counter and the shifted value of the branch counter to generate the source address which is in turn used to determine the reifetch address.

Abstract: A method and apparatus to determine readiness of a complex instruction for retirement includes decoding a complex instruction into a plurality of helper instructions; executing the plurality of helper instructions using an execution unit; indicating the plurality of helper instructions that are alive using a live instruction register; and maintaining a complex instruction identification for the complex instruction using a complex instruction identification register.

Abstract: A method and apparatus for processing instructions involves an instruction fetch unit arranged to receive a plurality of instructions. The instruction fetch unit includes a bypass buffer arranged to receive at least a portion of a plurality of instructions, and an output multiplexer arranged to receive the at least a portion of the plurality of instructions where the output multiplexer is arranged to output an instruction selected from one of an output of the bypass buffer and the at least a portion of the plurality of instructions.

Abstract: A method and apparatus for avoiding strand starvation is provided. The method and apparatus selectively switches from a first strand to a second strand dependent on a state of a computer system. The selectively switching is dependent on whether the second strand is alive and whether a value of a counter has reached a particular count.

Abstract: In an embodiment, the present invention describes a method and apparatus for detecting RAW condition earlier in an instruction pipeline. The store instructions are stored in a special store bypass buffer (SBB) within an instruction decode unit (IDU). The IDU compares the instruction fields that are used for address generation of all ‘load’ instructions against ‘store’ instructions within a group of fetched instructions and ‘store’ instructions previously stored in the SBB. If a match of instruction fields is found, the IDU ‘speculates’ that the load instruction has dependency on the ‘store’ instruction. A data cache unit (DCU) validates the dependency of the load instruction ‘speculated’ by the IDU. If a false dependency is ‘speculated’ by the IDU, the DCU forces a re-fetch of the load instruction.

Abstract: A register window fill technique for a retirement window having an entry size less than a number of fill instructions used in a fill condition is provided. The technique uses modified fill instructions that allow the retirement window to retire a portion of the fill instructions without having to determine whether a remaining portion of the fill instructions will execute without exceptions.

Abstract: A register window spill technique for an retirement window having an entry size less than a number of spill instructions used in a spill condition is provided. The technique uses modified spill instructions that allow the retirement window to retire a portion of the spill instructions without having to determine whether a remaining portion of the spill instructions will execute without exceptions.

Abstract: A technique for flattening architectural register windows into flattened space depending on a current window pointer to a register window is provided. The technique involves converting an n-bit value of a particular register in a register window to an x-bit value dependent on the current window pointer, where x is greater than n, and where the x-bit value is used for register dependency checking among a plurality of instructions.

Abstract: A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers holding physical vector elements, a mapping vector register holding a mapping vector, and a memory. The physical vector registers from nodes together form an architectural vector register having architectural vector elements. The mapping vector defines an assignment of architectural vector elements to physical vector elements for its node. The memories from the nodes together form an aggregate memory.

Abstract: A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers, and a memory. The physical vector registers from the nodes together form an architectural vector register, which are references by vector applications. Memories from nodes together form an aggregate memory. The vector applications load memory vector elements from the memories to the physical vector registers, and store physical vector elements from the physical vector registers to the memories. The memory vector elements are interleaved among the memories of the nodes to reduce inter-node traffic during the loads and the stores.