Abstract: A system includes a controller configured to receive a signal indicating whether a droop event has occurred. The system also includes a plurality of delay elements where each delay element of the plurality of delay elements responsive to a signal from the controller receives an input signal and outputs an output signal that is a delayed version of the input signal. At least one delay element of the plurality of delay elements receives a clocking signal as its input signal. The system also includes a selector configured to select rising edges and falling edges of output signals from the plurality of delay elements to form a modified clocking signal. The modified clocking signal is a modified version of the clocking signal.

Abstract: In a multi-node system, each node includes tiles. Each tile includes a cache controller, a local cache, and a snoop filter cache (SFC). The cache controller responsive to a memory access request by the tile checks the local cache to determine whether the data associated with the request has been cached by the local cache of the tile. The cached data from the local cache is returned responsive to a cache-hit. The SFC is checked to determine whether any other tile of a remote node has cached the data associated with the memory access request. If it is determined that the data has been cached by another tile of a remote node and if there is a cache-miss by the local cache, then the memory access request is transmitted to the global coherency unit (GCU) and the snoop filter to fetch the cached data. Otherwise an interconnected memory is accessed.

Abstract: Described herein are systems and methods for cache replacement mechanisms for speculative execution. For example, some systems include, a buffer comprising entries that are each configured to store a cache line of data and a tag that includes an indication of a status of the cache line stored in the entry, in an integrated circuit that is configured to: responsive to a cache miss caused by a load instruction that is speculatively executed by a processor pipeline, load a cache line of data corresponding to the cache miss into a first entry of the buffer and update the tag of the first entry to indicate the status is speculative; responsive to the load instruction being retired by the processor pipeline, update the tag to indicate the status is validated; and, responsive to the load instruction being flushed from the processor pipeline, update the tag to indicate the status is cancelled.

Abstract: A circuit provides for processing and routing peer-to-peer (P2P) traffic. A bus request queue store a data request received from a first peer device. A decoder compares an address portion of the data request against an address map to determine whether the data request is directed to either a second peer device or a local memory. A bus interface unit, in response to the data request being directed to the second peer device, 1) generates a memory access request from the bus request and 2) transmits the memory access request toward the second peer device via a bus. A memory controller, in response to the data request being directed to a local memory, accesses the local memory to perform a memory access operation based on the data request.

Abstract: A system includes a first counter configured to increment or decrement in response to a triggering event. The first counter is sized to overflow. The system also includes a second counter configured to increment or decrement in response to a triggering event. The first counter and the second counter are merged to form a third counter in response to detecting an overflow triggering event for the first counter. A merge bit indicative of whether the first counter and the second counter are merged changes value in response to merging the first counter and the second counter.

Abstract: Described herein are systems and methods for introducing noise in threaded execution to mitigate cross-thread monitoring. For example, some systems include an integrated circuit including a processor pipeline that is configured to execute instructions using an architectural state of a processor core; data storage circuitry configured to store a thread identifier; and a random parameter generator. The integrated circuit may be configured to: determine a time for insertion based on a random parameter generated using the random parameter generator; at the time for insertion, insert one or more instructions in the processor pipeline by participating in thread arbitration using the thread identifier; and execute the one or more instructions using one or more execution units of the processor pipeline.

Abstract: In a multi-node system, each node includes tiles. Each tile includes a cache controller, a local cache, and a snoop filter cache (SFC). The cache controller responsive to a memory access request by the tile checks the local cache to determine whether the data associated with the request has been cached by the local cache of the tile. The cached data from the local cache is returned responsive to a cache-hit. The SFC is checked to determine whether any other tile of a remote node has cached the data associated with the memory access request. If it is determined that the data has been cached by another tile of a remote node and if there is a cache-miss by the local cache, then the memory access request is transmitted to the global coherency unit (GCU) and the snoop filter to fetch the cached data. Otherwise an interconnected memory is accessed.

Abstract: A system includes a controller configured to receive a signal indicating whether a droop event has occurred. The system also includes a plurality of delay elements where each delay element of the plurality of delay elements responsive to a signal from the controller receives an input signal and outputs an output signal that is a delayed version of the input signal. At least one delay element of the plurality of delay elements receives a clocking signal as its input signal. The system also includes a selector configured to select rising edges and falling edges of output signals from the plurality of delay elements to form a modified clocking signal. The modified clocking signal is a modified version of the clocking signal.

Abstract: A system includes a controller configured to receive a signal indicating whether a droop event has occurred. The system also includes a plurality of delay elements where each delay element of the plurality of delay elements responsive to a signal from the controller receives an input signal and outputs an output signal that is a delayed version of the input signal. At least one delay element of the plurality of delay elements receives a clocking signal as its input signal. The system also includes a selector configured to select rising edges and falling edges of output signals from the plurality of delay elements to form a modified clocking signal. The modified clocking signal is a modified version of the clocking signal.

Abstract: A system includes a plurality of delay elements configured to receive an input clock signal. The system further includes an edge transition detector coupled to the plurality of delay elements. The plurality of delay elements is configured to detect the input clock signal transitioning from one value to another value. The system also includes a circuitry configured to determine a number of delay elements of the plurality of delay elements that the input clock signal propagates through prior to the input clock signal transitioning. The system also includes a logic or controller configured to determine whether a droop event has occurred based on the number of delay elements.

Abstract: A system includes a controller configured to receive a signal indicating whether a droop event has occurred. The system also includes a plurality of delay elements where each delay element of the plurality of delay elements responsive to a signal from the controller receives an input signal and outputs an output signal that is a delayed version of the input signal. At least one delay element of the plurality of delay elements receives a clocking signal as its input signal. The system also includes a selector configured to select rising edges and falling edges of output signals from the plurality of delay elements to form a modified clocking signal. The modified clocking signal is a modified version of the clocking signal.

Abstract: A system includes a plurality of delay elements configured to receive an input clock signal. The system further includes an edge transition detector coupled to the plurality of delay elements. The plurality of delay elements is configured to detect the input clock signal transitioning from one value to another value. The system also includes a circuitry configured to determine a number of delay elements of the plurality of delay elements that the input clock signal propagates through prior to the input clock signal transitioning. The system also includes a logic or controller configured to determine whether a droop event has occurred based on the number of delay elements.

Abstract: Instructions are executed in a pipeline of a processor, where each instruction is associated with a particular context. A first storage stores branch prediction information characterizing results of branch instructions previously executed. The first storage is dynamically partitioned into partitions of one or more entries. Dynamically partitioning includes updating a partition to include an additional entry by associating the additional entry with a particular subset of one or more contexts. A predicted branch result is determined based on at least a portion of the branch prediction information. An actual branch result provided based on an executed branch instruction is used to update the branch prediction information. Providing a predicted branch result for a first branch instruction includes retrieving a first entry from a first partition based at least in part on an identified first subset of one or more contexts associated with the first branch instruction.

Abstract: Instructions are executed in a pipeline of a processor, where each instruction is associated with a particular context. A first storage stores branch prediction information characterizing results of branch instructions previously executed. The first storage is dynamically partitioned into partitions of one or more entries. Dynamically partitioning includes updating a partition to include an additional entry by associating the additional entry with a particular subset of one or more contexts. A predicted branch result is determined based on at least a portion of the branch prediction information. An actual branch result provided based on an executed branch instruction is used to update the branch prediction information. Providing a predicted branch result for a first branch instruction includes retrieving a first entry from a first partition based at least in part on an identified first subset of one or more contexts associated with the first branch instruction.

Abstract: Techniques for tracking completion of transfer requests. In one embodiment, a compute node connects to a network adapter (NA). In one embodiment, software running on the compute node contains instructions in which some remote data transfer requests belong to (or are associated with) completion groups. These completion groups may be constructed so that the system may more efficiently determine the completion status of remote transfer requests. In one embodiment, The NA includes a hardware counter for each completion group (CG). In one embodiment, the counter is configured to count when each transfer request in the completion group is received and when each request in the completion group is completed. For example, the counter may increment on receipt and decrement on completion such that a zero indicates completion of all requests in the completion group. In one embodiment, the NA includes a flush register to indicate whether the counter is valid.

Abstract: A compute node with multiple transfer processes that share an Infiniband connection to send and receive messages across a network. Transfer processes are first associated with an Infiniband queue pair (QP) connection. Then send message commands associated with a transfer process are issued. This causes an Infiniband message to be generated and sent, via the QP connection, to a remote compute node corresponding to the QP. Send message commands associated with another process are also issued. This causes another Infiniband message to be generated and sent, via the same QP connection, to the same remote compute node. As mentioned, multiple processes may receive network messages received via a shared QP connection. A transfer process on a receiving compute node receives a network message through a QP connection using a receive queue. A second transfer process receives another message through the same QP connection using another receive queue.

Abstract: A server interconnect system includes a first server node operable to send and receive messages and a second server nodes operable to send and receive messages. The system further comprises a first interface unit in communication with the first server node and a second interface unit in communication with the second server node. The first interface unit has a first set of message send registers and a first set of message receive registers. Similarly, the second interface unit has a second set of message send registers and a second set of message receive registers. The server interconnect system also includes a communication switch that receives and routes a message from the first or second server nodes when either of the first or second registers indicates that a valid message is ready to be sent. A method implemented by the server interconnect system is also provided.

Abstract: Techniques for tracking completion of transfer requests. In one embodiment, a compute node connects to a network adapter (NA). In one embodiment, software running on the compute node contains instructions in which some remote data transfer requests belong to (or are associated with) completion groups. These completion groups may be constructed so that the system may more efficiently determine the completion status of remote transfer requests. In one embodiment, The NA includes a hardware counter for each completion group (CG). In one embodiment, the counter is configured to count when each transfer request in the completion group is received and when each request in the completion group is completed. For example, the counter may increment on receipt and decrement on completion such that a zero indicates completion of all requests in the completion group. In one embodiment, the NA includes a flush register to indicate whether the counter is valid.

Abstract: A system, comprising a compute node and coupled network adapter (NA), that supports improved data transfer request buffering and a more efficient method of determining the completion status of data transfer requests. Transfer requests received by the NA are stored in a first buffer then transmitted on a network interface. When significant network delays are detected and the first buffer is full, the NA sets a flag to stop software issuing transfer requests. Compliant software checks this flag before sending requests and does not issue further requests. A second NA buffer stores additional received transfer requests that were perhaps in-transit. When conditions improve the flag is cleared and the first buffer used again. Completion status is efficiently determined by grouping network transfer requests. The NA counts received requests and completed network requests for each group. Software determines if a group of requests is complete by reading a count value.

Abstract: A method for offloading computation flexibly to a communication adapter includes receiving a message that includes a procedure image identifier associated with a procedure image of a host application, determining a procedure image and a communication adapter processor using the procedure image identifier, and forwarding the first message to the communication adapter processor configured to execute the procedure image. The method further includes executing, on the communication adapter processor independent of a host processor, the procedure image in communication adapter memory by acquiring a host memory latch for a memory block in host memory, reading the memory block in the host memory after acquiring the host memory latch, manipulating, by executing the procedure image, the memory block in the communication adapter memory to obtain a modified memory block, committing the modified memory block to the host memory, and releasing the host memory latch.