Abstract: Disclosed embodiments provide techniques for improved performance in processing vector instructions. A processor core is accessed. The processor core is coupled to a memory hierarchy, and the processor core includes one or more vector execution units (VUs), and one or more load store units (LSUs). The processor core includes a vector register file (VRF). The VRF includes multiple vector registers, and each vector register includes multiple vector elements. Vector elements that have a source or destination in contiguous memory are identified. Load store units (LSUs) take advantage of the contiguous memory condition by executing a vector load or vector store operation as a single memory access, requiring a reduced number of clock cycles. The single memory access satisfies each memory operation for each vector element within the vector register file.

Abstract: Disclosed embodiments provide techniques for prefetching. A processor core that executes instructions out of order (OOO) is accessed. The processor core includes a local cache hierarchy, data prefetch logic, and a prefetch table and is coupled to an external memory system. A first load instruction with a first address is detected and causes a miss in the local cache hierarchy. Information pertaining to the first load instruction is saved in an entry of the prefetch table. The information includes the first address, a confidence count, and an out-of-order mask. A second load instruction with a second address is identified. The information is updated based on the detecting. The information is advanced. The second address is the next sequential address after the first address. The advancing is based on the detecting. One or more data prefetch instructions are issued to the second address plus an offset.

Abstract: Disclosed embodiments provide techniques for instruction execution with a processor pipeline for data transfer operations. A processor core is accessed. The processor core executes one or more instructions out of order. The processor core supports integer operations and floating-point operations. An instruction in the processor core is decoded. The instruction is a data transfer operation. The data transfer operation necessitates a floating-point operation and an integer operation. The floating-point operation and the integer operation are dispatched to one or more issue queues. The floating-point operation and the integer operation are interlocked. The interlocking is accomplished using at least one entry in the one or more issue queues. A first operation of the floating-point operation and the integer operation is executed. A second operation of the floating-point operation and the integer operation is executed. The execution of the second operation is based on the interlocking.

Abstract: Disclosed techniques enable vector instruction processing. A processor core is accessed. The processor core is coupled to a memory hierarchy, and is configured to execute vector operations, scalar operations, and micro-operations. A decode unit decodes a vector memory operation. The vector memory operation is associated with a unit stride addressing mode. The decoding includes dividing the vector memory operation into one or more vector memory micro-operations. A dispatch unit sends at least one vector micro-operation within the one or more vector micro-operations to a scalar request queue within a plurality of request queues. The at least one vector micro-operation is issued to a load-store unit within the processor core. The issuing includes selecting, from the plurality of request queues, the at least one vector memory micro-operation.

Abstract: Techniques for providing a return address stack with branch mispredict recovery are disclosed. A processor core is accessed. The processor core includes a return address stack (RAS), a local cache hierarchy, and branch prediction logic. RAS state information, including a write pointer, a read pointer, and a RAS count, is sent to a branch execution unit. One or more call instructions are detected in an instruction stream. The detecting generates a predicted return address for each of the one or more call instructions which are pushed on the RAS. The pushing is directed by the write pointer. One or more return instructions are recognized in the instruction stream. The write pointer and the read pointer for the RAS are updated, based on information from the branch execution unit. The predicted return address for each of the one or more return instructions is popped from the RAS.

Abstract: Disclosed embodiments provide techniques for prefetching. A processor core that executes instructions out of order (OOO) is accessed. The processor core includes a local cache hierarchy, data prefetch logic, and a prefetch table and is coupled to an external memory system. A first load instruction with a first address is detected and causes a miss in the local cache hierarchy. Information pertaining to the first load instruction is saved in an entry of the prefetch table. The information includes the first address, a confidence count, and an out-of-order mask. A second load instruction with a second address is identified. The information is updated based on the detecting. The information is advanced. The second address is the next sequential address after the first address. The advancing is based on the detecting. One or more data prefetch instructions are issued to the second address plus an offset.

Abstract: A processor core is accessed. The processor core includes a direct next program counter cache (DNPC) that includes multiple entries. The processor core executes a branch instruction associated with a program counter (PC) address. An entry within the DNPC that matches a tag associated with the PC address is found. An indirect bit within the matching entry is read. In cases where the indirect bit is not set, a branch target address for the branch instruction is produced by the DNPC. The DNPC generates a prediction for the branch instruction. The prediction is based on a local history register within the entry of the DNPC that matched the tag. A next PC address is determined, based on the branch target address that was produced and the prediction that was generated. The DNPC includes a plurality of prediction tables. Each prediction table is associated with each entry within the DNPC.

Abstract: Techniques for maintaining cache coherency while sharing data among multiple processors are disclosed. Multiple coherent elements are arranged in an M×N mesh topology. An element can include a compute coherency block (CCB), and a coherency ordering agent (COA). The COAs include a directory snoop filter (DSF), an eviction content addressable memory (eCAM), a miss and snoop queue (MSQ), and a pipeline logic. The CCB and COA include functions for interfacing with a hierarchical cache and directory snoop filter (DSF). A CCB from within one of the multiple coherent elements issues a read request. The corresponding directory snoop filter (DSF) is inspected to determine if there is a slot (way) available for storing information pertaining to the read request. In the event that no eligible vacancies are present in the DSF, a multi-pass process for handling a capacity limit in a DSF is performed.

Abstract: Techniques for debugging errors in a processor are disclosed. One or more processors are accessed. Each processor within the one or more processors includes a set of assertion registers. A processor within the one or more processors executes one or more instructions. An assertion logic detects an error condition in the processor. The detecting occurs during the executing. The error condition is recorded. The recording is based on one or more bits in the set of assertion registers. A hardware interface reads the one or more bits in the set of assertion registers. The one or more bits indicate the error condition to the hardware interface. The executing includes a communication protocol between the processor and a slave device. The error condition comprises an incorrect value in a credit buffer. The credit buffer controls a number of transactions allowed between the processor and the slave device.

Abstract: Disclosed embodiments provide techniques for malicious code detection in a processor core. A system-on-a-chip (SoC) is accessed. The SoC includes one or more processor cores. Each processor core is coupled to one or more external profiling agents (EPAs) on the SoC. An EPA configures a performance counter in a processor core within the SoC. The configuring is based on an offset value. The processor core updates the performance counter that was configured, based on a processor core event. A program state is saved to a performance counter storage area, based on a performance counter event. The program state that is saved corresponds to code being executed on the processor core. The program state is read from the performance counter storage area by the EPA. The EPA interprets the program state that was read, which identifies a malicious program running on the processor core.

Abstract: Disclosed embodiments provide techniques for branch prediction. A processor core is accessed. The processor core is coupled to memory and includes branch prediction circuitry. The branch prediction circuitry includes a branch target buffer (BTB) and an indirect branch target buffer (BTBI). A hashed program counter within the processor core is read. The BTB and BTBI are searched. The searching the BTB is accomplished with the hashed program counter and the searching the BTBI is accomplished with the hashed program counter and branch history information. A predicted branch target address within the BTBI or the BTB is matched. The matching within the BTBI is based on an indirect branch instruction, and the matching within the BTB is based on other branch instruction types. The predicted branch target address that was matched is predicted taken. The processor core is directed to fetch a next instruction from the predicted branch target address.

Abstract: Disclosed embodiments provide techniques for instruction execution with a processor pipeline for data transfer operations. A processor core is accessed. The processor core executes one or more instructions out of order. The processor core supports integer operations and floating-point operations. An instruction in the processor core is decoded. The instruction is a data transfer operation. The data transfer operation necessitates a floating-point operation and an integer operation. The floating-point operation and the integer operation are dispatched to one or more issue queues. The floating-point operation and the integer operation are interlocked. The interlocking is accomplished using at least one entry in the one or more issue queues. A first operation of the floating-point operation and the integer operation is executed. A second operation of the floating-point operation and the integer operation is executed. The execution of the second operation is based on the interlocking.

Abstract: A processor core includes a local cache hierarchy, prefetch logic, and a prefetch table, where the processor core is coupled to an external memory system. A data stream is detected, where the data stream includes multiple load instructions, including a load instruction that causes a cache miss, resulting in prefetching. A prefetch table is initialized with information pertaining to load instructions, and includes a Positive or Negative value (PON), a stride, and a saturation count. Information in the prefetch table is updated as new load instructions are prefetched. An underlying stride of the data stream is discovered, based on the updating. Data is prefetched using an offset, where a polarity of the offset is based on the PON, enabling effective stride detection with dynamic directionality and out-of-order instructions.

Abstract: Disclosed embodiments provide techniques for enhancing security of a processor. Multiple consistency units are distributed within a processor core. Instructions are executed in an architecturally defined mode. The architecturally defined mode can be based on an instruction set architecture (ISA). In response to detecting an error in at least one consistency unit, disclosed embodiments reduce the functionality of the processor core. The reduced functionality includes halting the processor core, shutting down the processor core, switching the functionality of the processor core to a safe mode, and/or other suitable actions. The consistency unit can include a program counter comparison function. The consistency unit can include a completion signal check function. The consistency unit can include an address check function. The consistency unit can include a temporal proximity check function. Disclosed embodiments provide safeguards against various environmental attacks, such as voltage and/or clock alterations.

Abstract: Techniques for providing a return address stack with branch mispredict recovery are disclosed. A processor core is accessed. The processor core includes a return address stack (RAS), a local cache hierarchy, and branch prediction logic. RAS state information, including a write pointer, a read pointer, and a RAS count, is sent to a branch execution unit. One or more call instructions are detected in an instruction stream. The detecting generates a predicted return address for each of the one or more call instructions which are pushed on the RAS. The pushing is directed by the write pointer. One or more return instructions are recognized in the instruction stream. The write pointer and the read pointer for the RAS are updated, based on information from the branch execution unit. The predicted return address for each of the one or more return instructions is popped from the RAS.

Abstract: Techniques for performance profiling based on processor performance profiling using agents are disclosed. A processor core is accessed. The processor core includes a performance counter, a performance counter storage area, and a performance counter control register. The processor core includes a performance monitoring interface. The performance counter, performance counter storage area, and performance counter control register are assigned to an external profiling agent, which loads the performance counter and the performance counter control register. The loading is based on a particular event in the processor core. A program state is saved to the storage area, based on a counter event in the performance counter and an enable bit in the performance counter control register being set. The program state that is saved corresponds to code being executed on the processor core. The program state is read, from the storage area, by the external profiling agent.

Abstract: Disclosed embodiments provide techniques for data prefetching. A processor core is accessed. The processor core includes prefetch logic and a local cache hierarchy and is coupled to a memory system. A stride of a data stream is detected. The data stream comprises two or more load instructions that cause two or more misses in the local cache hierarchy. Information about the data stream is accumulated. The information includes a stride count. Prefetch operations to the memory system are generated, based on the information. The prefetch operations include prefetch addresses. A rate of the prefetch operations is limited, based on the stride count. Based on the stride count, the prefetcher can enter a saturation state. The saturation state keeps the cache supplied with prefetched data. A number of stride prefetch operations is based on the stride of the data stream. The number is stored in a software-updatable configuration register array.

Abstract: Disclosed embodiments provide techniques for branch prediction. A processor core is accessed. The processor core is coupled to memory and includes branch prediction circuitry. The branch prediction circuitry includes a branch target buffer (BTB) and an indirect branch target buffer (BTBI). A hashed program counter within the processor core is read. The BTB and BTBI are searched. The searching the BTB is accomplished with the hashed program counter and the searching the BTBI is accomplished with the hashed program counter and branch history information. A predicted branch target address within the BTBI or the BTB is matched. The matching within the BTBI is based on an indirect branch instruction, and the matching within the BTB is based on other branch instruction types. The predicted branch target address that was matched is predicted taken. The processor core is directed to fetch a next instruction from the predicted branch target address.

Abstract: Techniques for instruction execution based on processor instruction exception handling are disclosed. A processor core is accessed. The processor core executes at least one instruction thread. The processor core executes one or more instructions out of order. An ordered list of instructions is maintained. The ordered list is based on instructions that are presented to the processor core for execution. The ordered list is organized using one or more pointers. An execution exception is detected in the processor core. The execution exception corresponds to one of the instructions in the ordered list. The execution exception requires initiating an exception handling routine. An effective age of an instruction in the ordered list is determined. The effective age corresponds to the execution exception. The exception handling routine is initiated, based on matching the effective age of an instruction in the ordered list with one of the one or more pointers.

Abstract: A system includes a controller configured to receive a signal indicating whether a droop event has occurred. The system also includes a plurality of delay elements where each delay element of the plurality of delay elements responsive to a signal from the controller receives an input signal and outputs an output signal that is a delayed version of the input signal. At least one delay element of the plurality of delay elements receives a clocking signal as its input signal. The system also includes a selector configured to select rising edges and falling edges of output signals from the plurality of delay elements to form a modified clocking signal. The modified clocking signal is a modified version of the clocking signal.