Patents by Inventor Rabindra Roy

Rabindra Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks
    Patent number: 7225423
    Abstract: A system and method for designing ICs, including the steps of: analyzing and optimizing a target IC design based on design-specific objectives; partitioning the optimized target IC design into pre-defined standard-cells from one or more libraries and creating design-specific cells specifically having unique functionality and characteristics not found amongst the standard-cells; identifying and determining a minimal subset of the standard-cells and design-specific cells, the interconnection of which represents the target IC design; generating the necessary views, including layout and characterizing of the design-specific cells included in a unique, minimal subset, wherein the IC design is subject to objectives and constraints of the target IC.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: May 29, 2007
    Assignee: Zenasis Technologies, Inc.
    Inventors: Debashis Bhattacharya, Vamsi Boppana, Rabindra Roy, Jayanta Roy
  • Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process
    Patent number: 7003738
    Abstract: The present invention pertains to an automated method for designing a integrated circuit (IC) design-specific cell, the method includes the steps of receiving a design specification for the design-specific cell, mapping a transistor-level representation of the design-specific cell, wherein the mapping is based on at least one, but perhaps plural design specifications, and evaluating the transistor-level representation of the design-specific cell for satisfaction of the design specification.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: February 21, 2006
    Assignee: Zenasis Technologies, Inc.
    Inventors: Debashis Bhattacharya, Vamsi Boppana, Rajeev Murgai, Rabindra Roy
  • Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS
    Publication number: 20020053063
    Abstract: The present invention pertains to an automated method for designing a integrated circuit (IC) design-specific cell, the method includes the steps of receiving a design specification for the design-specific cell, mapping a transistor-level representation of the design-specific cell, wherein the mapping is based on at least one, but perhaps plural design specifications, and evaluating the transistor-level representation of the design-specific cell for satisfaction of the design specification.
    Type: Application
    Filed: June 29, 2001
    Publication date: May 2, 2002
    Applicant: Zenasis Technologies, Inc.
    Inventors: Debashis Bhattacharya, Vamsi Boppana, Rajeev Murgai, Rabindra Roy
  • Process for the preparation of an extract from human placenta containing glycosphingolipids and endothelin-like constituent peptides useful for the treatment of vitiligo
    Patent number: 5690966
    Abstract: A process for the preparation of an extract from human placenta containing glycosphingolipids and endothelin-like peptides useful for the treatment of vitiligo is disclosed.
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: November 25, 1997
    Assignee: Council of Scientific & Industrial Research
    Inventors: Ranjan Bhadra, Prajnamoy Pal, Rabindra Roy, Ajit Kumar Dutta