Patents by Inventor Rachael J. Parker
Rachael J. Parker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11720672Abstract: The disclosure generally provides methods, systems and apparatus for an improved a Physically Unclonable Function (PUF). In one embodiment, the disclosure relates to a method to provide data from a Physically Unclonable Function (PUF) circuit array. The method includes storing a plurality of first data bits into a respective ones of a plurality of first bitcells of the PUF array to form a first dataset; storing a plurality of second data bits into a respective ones of a plurality of second bitcells of the PUF array, the plurality of second data bits defining a helper dataset; reading the first dataset from the plurality of first bitcells to provide a first read dataset; applying an error correction factor to the first read data dataset to form a security key dataset; and outputting the security key dataset from the PUF circuit array.Type: GrantFiled: April 25, 2022Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Kuan-Yueh Shen, David Johnston, Rachael J. Parker, Javier Dacuna Santos
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Publication number: 20230187371Abstract: A microelectronic assembly is provided, comprising: a first plurality of integrated circuit (IC) dies in a first level, each one of the first plurality of IC dies having respective first physical unclonable function (PUF) circuits; a second IC die having a second PUF circuit and a security circuit; a second plurality of IC dies in a second level, the second level not coplanar with the first level, the first level and the second level being coupled with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects; and conductive pathways between the first plurality of IC dies and the second IC die for communication between the first PUF circuits and the second PUF circuit, the conductive pathways comprising a portion of the interconnects.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Applicant: Intel CorporationInventors: Rachael J. Parker, David Johnston, Georgios Dogiamis
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Publication number: 20220253525Abstract: The disclosure generally provides methods, systems and apparatus for an improved a Physically Unclonable Function (PUF). In one embodiment, the disclosure relates to a method to provide data from a Physically Unclonable Function (PUF) circuit array. The method includes storing a plurality of first data bits into a respective ones of a plurality of first bitcells of the PUF array to form a first dataset; storing a plurality of second data bits into a respective ones of a plurality of second bitcells of the PUF array, the plurality of second data bits defining a helper dataset; reading the first dataset from the plurality of first bitcells to provide a fist read dataset; applying an error correction factor to the first read data dataset to form a security key dataset; and outputting the security key dataset from the PUF circuit array.Type: ApplicationFiled: April 25, 2022Publication date: August 11, 2022Applicant: Intel CorporationInventors: Kuan-Yueh Shen, David Johnston, Rachael J. Parker, Javier Dacuna Santos
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Patent number: 11321459Abstract: The disclosure generally provides methods, systems and apparatus for an improved a Physically Unclonable Function (PUF). In one embodiment, the disclosure relates to a method to provide data from a Physically Unclonable Function (PUF) circuit array. The method includes storing a plurality of first data bits into a respective ones of a plurality of first bitcells of the PUF array to form a first dataset; storing a plurality of second data bits into a respective ones of a plurality of second bitcells of the PUF array, the plurality of second data bits defining a helper dataset; reading the first dataset from the plurality of first bitcells to provide a first read dataset; applying an error correction factor to the first read data dataset to form a security key dataset; and outputting the security key dataset from the PUF circuit array.Type: GrantFiled: December 27, 2018Date of Patent: May 3, 2022Assignee: INTEL CORPORATIONInventors: Kuan-Yueh Shen, David Johnston, Rachael J. Parker, Javier Dacuna Santos
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Patent number: 10656916Abstract: Embodiments include apparatuses, methods, and systems for a random number generator that includes an entropy source. The entropy source may be coupled to a deterministic feedback circuit and a stochastic feedback circuit. The deterministic feedback circuit may include detection logic to detect when a bit of the output signal of the entropy source has registered, a pre-delay feedback path to cause the entropy source to power off responsive to the detection, and a post-delay feedback path to cause the entropy source to power on, after the entropy source is powered off, to generate a second bit of the output signal. The post-delay feedback path may include one or more delay cells that are bypassed by the pre-delay feedback path. Other circuits and techniques related to random number generators are also described. Further embodiments may be described and/or claimed.Type: GrantFiled: December 27, 2018Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Rachael J. Parker, Calvin Chiem
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Publication number: 20190205098Abstract: Embodiments include apparatuses, methods, and systems for a random number generator that includes an entropy source. The entropy source may be coupled to a deterministic feedback circuit and a stochastic feedback circuit. The deterministic feedback circuit may include detection logic to detect when a bit of the output signal of the entropy source has registered, a pre-delay feedback path to cause the entropy source to power off responsive to the detection, and a post-delay feedback path to cause the entropy source to power on, after the entropy source is powered off, to generate a second bit of the output signal. The post-delay feedback path may include one or more delay cells that are bypassed by the pre-delay feedback path. Other circuits and techniques related to random number generators are also described. Further embodiments may be described and/or claimed.Type: ApplicationFiled: December 27, 2018Publication date: July 4, 2019Inventors: Rachael J. Parker, Calvin Chiem
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Publication number: 20190130103Abstract: The disclosure generally provides methods, systems and apparatus for an improved a Physically Unclonable Function (PUF). In one embodiment, the disclosure relates to a method to provide data from a Physically Unclonable Function (PUF) circuit array. The method includes storing a plurality of first data bits into a respective ones of a plurality of first bitcells of the PUF array to form a first dataset; storing a plurality of second data bits into a respective ones of a plurality of second bitcells of the PUF array, the plurality of second data bits defining a helper dataset; reading the first dataset from the plurality of first bitcells to provide a fist read dataset; applying an error correction factor to the first read data dataset to form a security key dataset; and outputting the security key dataset from the PUF circuit array.Type: ApplicationFiled: December 27, 2018Publication date: May 2, 2019Applicant: Intel CorporationInventors: Kuan-Yueh Shen, David Johnston, Rachael J. Parker, Javier Dacuna Santos
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Patent number: 10168994Abstract: Embodiments include apparatuses, methods, and systems for a random number generator that includes an entropy source. The entropy source may be coupled to a deterministic feedback circuit and a stochastic feedback circuit. The deterministic feedback circuit may include detection logic to detect when a bit of the output signal of the entropy source has registered, a pre-delay feedback path to cause the entropy source to power off responsive to the detection, and a post-delay feedback path to cause the entropy source to power on, after the entropy source is powered off, to generate a second bit of the output signal. The post-delay feedback path may include one or more delay cells that are bypassed by the pre-delay feedback path. Other circuits and techniques related to random number generators are also described. Further embodiments may be described and/or claimed.Type: GrantFiled: April 11, 2017Date of Patent: January 1, 2019Assignee: Intel CorporationInventors: Rachael J. Parker, Calvin Chiem
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Publication number: 20180293053Abstract: Embodiments include apparatuses, methods, and systems for a random number generator that includes an entropy source. The entropy source may be coupled to a deterministic feedback circuit and a stochastic feedback circuit. The deterministic feedback circuit may include detection logic to detect when a bit of the output signal of the entropy source has registered, a pre-delay feedback path to cause the entropy source to power off responsive to the detection, and a post-delay feedback path to cause the entropy source to power on, after the entropy source is powered off, to generate a second bit of the output signal. The post-delay feedback path may include one or more delay cells that are bypassed by the pre-delay feedback path. Other circuits and techniques related to random number generators are also described. Further embodiments may be described and/or claimed.Type: ApplicationFiled: April 11, 2017Publication date: October 11, 2018Inventors: Rachael J. Parker, Calvin Chiem
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Patent number: 9391617Abstract: An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a hardware-embedded key upon power-up that is unique to the combination of random variations of selected IC cells, resistant to tampering prior to and during manufacture, and tolerant to aging, instantaneous thermal noise, and environmental variations, such as voltage and temperature fluctuations. The key may be used as, without limitation, a Platform Root Key, a High-Bandwidth Digital Content Protection (HDCP) key, an Enhanced Privacy Identification (EPID) key, and/or an Advanced Access Content System (AACS) key. Also disclosed are techniques to measure stability and stress-harden an IC cell based on output states of the IC cell.Type: GrantFiled: May 8, 2013Date of Patent: July 12, 2016Assignee: Intel CorporationInventors: Sanu K. Mathew, Rachael J. Parker, Ram K. Krishnamurthy
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Patent number: 9264048Abstract: An integrated circuit includes a programmable logic device and optionally a control circuit coupled to the programmable logic device (PLD). The control circuit may detect that a reconfiguration criterion is satisfied. Responsive to the reconfiguration criterion being satisfied, the control logic may configure, using one or more randomizations, the PLD to implement a secret operation, wherein a first randomized configuration of the PLD results in a first circuit implementation that is different from, but functionally equivalent to, a second circuit implementation that results from a second randomized configuration of the PLD.Type: GrantFiled: December 18, 2013Date of Patent: February 16, 2016Assignee: Intel CorporationInventor: Rachael J. Parker
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Publication number: 20150171870Abstract: An integrated circuit includes a programmable logic device and optionally a control circuit coupled to the programmable logic device (PLD). The control circuit may detect that a reconfiguration criterion is satisfied. Responsive to the reconfiguration criterion being satisfied, the control logic may configure, using one or more randomizations, the PLD to implement a secret operation, wherein a first randomized configuration of the PLD results in a first circuit implementation that is different from, but functionally equivalent to, a second circuit implementation that results from a second randomized configuration of the PLD.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Inventor: Rachael J. Parker
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Publication number: 20140266297Abstract: An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a hardware-embedded key upon power-up that is unique to the combination of random variations of selected IC cells, resistant to tampering prior to and during manufacture, and tolerant to aging, instantaneous thermal noise, and environmental variations, such as voltage and temperature fluctuations. The key may be used as, without limitation, a Platform Root Key, a High-Bandwidth Digital Content Protection (HDCP) key, an Enhanced Privacy Identification (EPID) key, and/or an Advanced Access Content System (AACS) key. Also disclosed are techniques to measure stability and stress-harden an IC cell based on output states of the IC cell.Type: ApplicationFiled: May 8, 2013Publication date: September 18, 2014Inventors: Sanu K. Mathew, Rachael J. Parker, Ram K. Krishnamurthy
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Patent number: 7231552Abstract: A JTAG-compatible device includes a unique identifier stored in dedicated non-volatile memory, a test access port (TAP) controller, a TAP instruction register, a dedicated data register, and a comparison block. The TAP instruction register enables and/or disables TAP instruction execution by the device. The dedicated data register is of a length that is the same or a subset of the length of the unique identifier. The comparison block can be an arithmetic logic unit (ALU) or other circuitry that compares a code scanned into the dedicated data register with the unique identifier stored in a PROM. The TAP controller can selectively ignore TAP commands if a code scanned into dedicated data register does not match the stored unique identifier. This allows the TAP controller to conditionally or independently control several devices that are connected in parallel. The unique identifier can be device-specific, device type-specific, and/or device configuration specific.Type: GrantFiled: October 24, 2002Date of Patent: June 12, 2007Assignee: Intel CorporationInventors: Rachael J. Parker, Gregory M. Iovino
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Method and apparatus to construct a fifty percent (50%) duty cycle clock signal across power domains
Patent number: 7157950Abstract: Some microprocessors are designed such that the microprocessor core clock has a duty cycle of approximately fifty percent. When a clock signal propagates across power domains the clock signal pulse shape will change. The rising edges and falling edges of the clock signal will become asymmetrical (e.g., the duty cycle is no longer fifty percent). According to embodiments of the present invention, a parallel divide function is applied to a clock signal having a frequency f and its complement. The resulting four signals (i.e., f/2, its complement, f/2 at ninety degrees out of phase from f/2 and its complement) are applied to an XOR gate that combines them to generate a clock signal that has a duty cycle of approximately fifty percent and a frequency f, which is the same as the input clock signal.Type: GrantFiled: June 20, 2003Date of Patent: January 2, 2007Assignee: Intel CorporationInventors: Hon-Mo Raymond Law, Rachael J. Parker -
Patent number: 7049865Abstract: Embodiments of the present invention include a circuit, a method, and a system for power-on detect circuitry for use with multiple voltage domains.Type: GrantFiled: March 5, 2004Date of Patent: May 23, 2006Assignee: Intel CorporationInventors: Rachael J. Parker, Mark L. Neidengard, Patrick J. Ott, Gregory F. Taylor
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Patent number: 7038508Abstract: Embodiments of the present invention describe methods and apparatuses for detecting signal loss in circuits such as a phase-locked loop (PLL). In one embodiment a PLL is equipped with detection logic to detect loss of a reference clock provided to the PLL and a feedback clock generated by the PLL.Type: GrantFiled: April 30, 2004Date of Patent: May 2, 2006Assignee: Intel CorporationInventors: Rachael J. Parker, Hon-Mo Raymond Law, Timothy D. Low
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Method and apparatus to construct a fifty percent (50%) duty cycle clock signal across power domains
Publication number: 20040260963Abstract: Some microprocessors are designed such that the microprocessor core clock has a duty cycle of approximately fifty percent. When a clock signal propagates across power domains the clock signal pulse shape will change. The rising edges and falling edges of the clock signal will become asymmetrical (e.g., the duty cycle is no longer fifty percent). According to embodiments of the present invention, a parallel divide function is applied to a clock signal having a frequency f and its complement. The resulting four signals (i.e., f/2, its complement, f/2 at ninety degrees out of phase from f/2 and its complement) are applied to an XOR gate that combines them to generate a clock signal that has a duty cycle of approximately fifty percent and a frequency f, which is the same as the input clock signal.Type: ApplicationFiled: June 20, 2003Publication date: December 23, 2004Inventors: Hon-Mo Raymond Law, Rachael J. Parker -
Publication number: 20040083414Abstract: A JTAG-compatible device includes a unique identifier stored in dedicated non-volatile memory, a test access port (TAP) controller, a TAP instruction register, a dedicated data register, and a comparison block. The TAP instruction register enables and/or disables TAP instruction execution by the device. The dedicated data register is of a length that is the same or a subset of the length of the unique identifier. The comparison block can be an arithmetic logic unit (ALU) or other circuitry that compares a code scanned into the dedicated data register with the unique identifier stored in a PROM. The TAP controller can selectively ignore TAP commands if a code scanned into dedicated data register does not match the stored unique identifier. This allows the TAP controller to conditionally or independently control several devices that are connected in parallel. The unique identifier can be device-specific, device type-specific, and/or device configuration specific.Type: ApplicationFiled: October 24, 2002Publication date: April 29, 2004Inventors: Rachael J. Parker, Gregory M. Iovino
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Patent number: 6469533Abstract: An integrated circuit includes a first circuit, a second circuit, at least one test pad and multiplexing circuitry. The second circuit is coupled to the first circuit and has substantially the same design as the first circuit to emulate an electrical characteristic of the first circuit. The multiplexing circuitry selectively couples the test pad(s) to the second circuit to selectively measure the electrical characteristic.Type: GrantFiled: April 10, 2000Date of Patent: October 22, 2002Assignee: Intel CorporationInventors: Nasser A. Kurd, Keng L. Wong, Rachael J. Parker, Hung-Piao Ma