Patents by Inventor Rachel A. Steinhardt
Rachel A. Steinhardt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120415Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.Type: ApplicationFiled: October 1, 2022Publication date: April 11, 2024Applicant: Intel CorporationInventors: Scott B. Clendenning, Sudarat Lee, Kevin P. O'Brien, Rachel A. Steinhardt, John J. Plombon, Arnab Sen Gupta, Charles C. Mokhtarzadeh, Gauri Auluck, Tristan A. Tronic, Brandon Holybee, Matthew V. Metz, Dmitri Evgenievich Nikonov, Ian Alexander Young
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Publication number: 20240113212Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Kevin P. O'Brien, Scott B. Clendenning, Tristan A. Tronic, Dominique A. Adams, Carly Rogan, Hai Li, Arnab Sen Gupta, Gauri Auluck, I-Cheng Tung, Brandon Holybee, Rachel A. Steinhardt, Punyashloka Debashis
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Publication number: 20240113220Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Arnab Sen Gupta, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Uygar E. Avci, Kevin P. O'Brien, Scott B. Clendenning, Jason C. Retasket, Shriram Shivaraman, Dominique A. Adams, Carly Rogan, Punyashloka Debashis, Brandon Holybee, Rachel A. Steinhardt, Sudarat Lee
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Publication number: 20240105822Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and theType: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Kevin P. O'Brien, Brandon Holybee, Carly Rogan, Dmitri Evgenievich Nikonov, Punyashloka Debashis, Rachel A. Steinhardt, Tristan A. Tronic, Ian Alexander Young, Marko Radosavljevic, John J. Plombon
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Publication number: 20240105810Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Rachel A. Steinhardt, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Kevin P. O'Brien, Scott B. Clendenning, Tristan A. Tronic, Dominique A. Adams, Carly Rogan, Arnab Sen Gupta, Brandon Holybee, Punyashloka Debashis, I-Cheng Tung, Gauri Auluck
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Publication number: 20240097031Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Applicant: Intel CorporationInventors: Punyashloka Debashis, Rachel A. Steinhardt, Brandon Holybee, Kevin P. O'Brien, Dmitri Evgenievich Nikonov, John J. Plombon, Ian Alexander Young, Raseong Kim, Carly Rogan, Dominique A. Adams, Arnab Sen Gupta, Marko Radosavljevic, Scott B. Clendenning, Gauri Auluck, Hai Li, Matthew V. Metz, Tristan A. Tronic, I-Cheng Tung
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Publication number: 20230411390Abstract: In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC).Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Applicant: Intel CorporationInventors: Kevin P. O'Brien, Ande Kitamura, Ashish Verma Penumatcha, Carl Hugo Naylor, Kirby Maxey, Rachel A. Steinhardt, Scott B. Clendenning, Sudarat Lee, Uygar E. Avci, Chelsey Dorow
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Publication number: 20230353157Abstract: Magnetoelectric spin-orbit logic (MESO) devices comprise a magnetoelectric switch capacitor coupled to a spin-orbit coupling structure. The logic state of the MESO device is represented by the magnetization orientation of the ferromagnet of the magnetoelectric switch capacitor and the spin-orbit coupling structure converts the magnetization orientation of the ferromagnet to an output current. MESO devices in which all or at least some of the constituent layers of the device are perovskite materials can provide advantages such as improved control over the manufacturing of MESO devices and high quality interfaces between MESO layers due to the lattice matching of perovskite materials.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Inventors: Tanay A. Gosavi, Chia-Ching Lin, Sasikanth Manipatruni, Dmitri Evgenievich Nikonov, Ian Alexander Young, Ramamoorthy Ramesh, Darrell G. Schlom, Megan E. Holtz, Rachel A. Steinhardt
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Patent number: 11678587Abstract: A ferroelectric device includes a substrate, a first electrode on the substrate, and a hexagonal ferroelectric material on the first electrode. The first electrode comprises a single crystal epitaxial material. By using a single crystal epitaxial material for an electrode to a hexagonal ferroelectric material, a high-quality material interface may be provided between these layers, thereby improving the performance of the ferroelectric device by allowing for a reduced coercive field.Type: GrantFiled: October 21, 2020Date of Patent: June 13, 2023Assignee: Cornell UniversityInventors: Darrell Schlom, Rachel Steinhardt, Megan Holtz
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Patent number: 11276728Abstract: A heterostructure includes a substrate exhibiting a piezoelectric effect, and a magnetostrictive film supported by the substrate. The magnetostrictive film includes an iron-gallium alloy. The iron-gallium alloy has a gallium composition greater than 20%.Type: GrantFiled: February 7, 2020Date of Patent: March 15, 2022Assignees: The Regents of the University of Michigan, Cornell UniversityInventors: John Thomas Heron, Peter Benjamin Meisenheimer, Darrell G. Schlom, Rachel Steinhardt
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Publication number: 20210249468Abstract: A heterostructure includes a substrate exhibiting a piezoelectric effect, and a magnetostrictive film supported by the substrate. The magnetostrictive film includes an iron-gallium alloy. The iron-gallium alloy has a gallium composition greater than 20%.Type: ApplicationFiled: February 7, 2020Publication date: August 12, 2021Inventors: John Thomas Heron, Peter Benjamin Meisenheimer, Darrell G. Schlom, Rachel Steinhardt
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Publication number: 20210119112Abstract: A ferroelectric device includes a substrate, a first electrode on the substrate, and a hexagonal ferroelectric material on the first electrode. The first electrode comprises a single crystal epitaxial material. By using a single crystal epitaxial material for an electrode to a hexagonal ferroelectric material, a high-quality material interface may be provided between these layers, thereby improving the performance of the ferroelectric device by allowing for a reduced coercive field.Type: ApplicationFiled: October 21, 2020Publication date: April 22, 2021Inventors: Darrell Schlom, Rachel Steinhardt, Megan Holtz