Abstract: Methods of verifying a property of a hardware design for an integrated circuit to implement a product of power functions of the form x0t0× . . . ×xntn, wherein t0 . . . tn are fixed, rational numbers, x0 . . . xn are floating point inputs, and n is an integer greater than or equal to one. A first verification phase comprises formally verifying that, for any first non-exception input set X=X0, . . . , Xn and any second non-exception input set Y=Y0, . . . , Yn in an input space wherein corresponding inputs have a same mantissa and (t0X0.exp+ . . . +tnXn.exp)?(t0Y0.exp+ . . . +tnYn.exp) is an integer, an instantiation of the hardware design generates outputs X? and Y? with a same mantissa and X?exp?(t0X0.exp+ . . . +tnXn.exp)=Y?exp?(t0Y0.exp+ . . . +tnYn.exp); and second verification phase comprises verifying the property for the hardware design for a subset of input sets in the input space, the subset of input sets selected based on exponents sets wherein (t0X0.exp+ . . . +tnXn.exp)?(t0Y0.exp+ . . . +tnYn.

Abstract: A hardware design for a component that evaluates a main algebraic expression comprising at least two variables is verified, the main algebraic expression being representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. An instantiation of the hardware design is verified as correctly evaluating each of the plurality of sub-algebraic expressions, and the instantiation of the hardware design is formally evaluated as correctly evaluating one or more combinations of sub-algebraic expressions, wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.

Abstract: A hardware design for a component that evaluates a main algebraic expression comprising at least two variables is verified, the main algebraic expression being representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. An instantiation of the hardware design is verified as correctly evaluating each of the plurality of sub-algebraic expressions, and the instantiation of the hardware design is formally evaluated as correctly evaluating one or more combinations of sub-algebraic expressions, wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.

Abstract: Methods and systems for verifying a hardware design for a component that evaluates a main algebraic expression comprising at least two variables wherein the main algebraic expression is representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions.

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant kth difference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the kth difference is predetermined and e is equal to k+1 when the value of the kth difference is not predetermined.

Abstract: Methods and systems for verifying a hardware design for a component that evaluates a main algebraic expression comprising at least two variables wherein the main algebraic expression is representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions.