Abstract: Detecting locking discipline violations on shared resources. For example, a method of detecting locking discipline violations of shared resources of a computing platform, by a testing process to be executed concurrently with one or more other processes on said computing platform, the testing process comprising: locking a shared resource of said computing platform; reading a value of the shared resource; locally storing the value of the shared resource; rereading the value of the shared resource after a predefined time period; and generating a locking discipline violation report if the value of said shared resource as reread by said rereading is different from the value of said resource as locally stored by said locally storing.

Abstract: A method for modeling a test space comprising defining a coverage model including: one or more variables, wherein respective values for the variables are assigned, and restrictions based on which valid variable value combinations are determined for the purpose of testing the model, wherein at least two values that are assignable to the one or more variables are merged to reduce number of variable values in the coverage model.

Abstract: Obtaining a functional coverage model of a System Under Test (SUT) defining all functional coverage tasks of the SUT, wherein the functional coverage model defining a test-space with respect to functional attributes; obtaining a set of covered functional coverage tasks; encoding a covered Binary Decision Diagram (BDD) to represent the set of covered functional coverage tasks within the test-space; and manipulating the covered BDD to identify one or more coverage holes, wherein a coverage hole defines a set of coverage tasks in the test-space, all having a same combination of values to a subset of the functional attributes, that are not covered by the set of covered functional coverage task.

Abstract: A method for modeling test space for verifying system behavior is provided. The method comprises defining a coverage model based on one or more variables, wherein respective value combinations for the variables are assigned to define a test space for a system under test, and zero or more constraints define restrictions on value combinations assigned to the variables, wherein the restrictions define whether said value combinations are valid; and designating, as interchangeable, relevant variables values in the coverage model.

Abstract: A method for modeling a test space is provided. The method comprises defining a coverage model including: one or more variables, wherein respective values for the variables are assigned, and one or more definitions for value combinations for said variables with assigned values, wherein at least one of said value combinations is defined as optional, and zero or more other said value combinations are defined as forbidden or mandatory for purpose of generating test scenarios to test a system for which the coverage model is defined.

Abstract: A method for refining a test plan is provided. The method comprises defining a coverage model including: one or more variables, wherein respective values for the variables are assigned, and one or more definitions for value combinations for said variables with assigned values, wherein zero or more of said value combinations are defined according to one or more restrictions for the purpose of generating a test plan to test a system for which the coverage model is constructed; determining zero or more uncovered value combinations in the test plan; and providing means to update the test plan.

Abstract: Device, system, and method of debugging computer programs. For example, a method for debugging computer programs includes: locating a bug in a computer program based on a first score corresponding to a first instrumentation location of the computer program and a second score corresponding to a second instrumentation location of the computer program.

Abstract: A method for enhancing synchronization coverage for a logic code is provided. The method comprises tracking whether one or more code sections in the logic code are blocked by at least another code section in the logic code, or whether one or more code sections in the logic code are blocking at least another code section in the logic code, during one or more test runs; and including one or more delay mechanisms in the logic code to introduce a delay in execution of a first code section in the logic code, wherein length of introduced delay is dependent on whether the first code section was blocked by a second code section or whether the first code section was blocking the second code section.

Abstract: A computer-implemented method, apparatus, and computer program product for assisting in dynamic verification of a System Under Test (SUT). The method comprising obtaining a set of functional attributes and associated domains with respect to a System Under Test (SUT), and obtaining a set of restrictions over the functional attributes and associated domains. The method comprising encoding a Binary Decision Diagram (BDD) to represent a Cartesian cross-product test-space of all possible combinations of values of the functional attributes excluding combinations that are restricted by the set of restrictions, whereby the BDD symbolically represents the Cartesian cross-product test-space. The method may further comprise analyzing the Cartesian cross-product test-space by manipulating the BDD so as to assist in performing dynamic verification of the SUT.

Abstract: Systems and methods for modeling test space for verifying system behavior, using one or more auxiliary variables, are provided. The method comprises implementing a functional coverage model including: one or more attributes, wherein respective values for the attributes are assigned according to a test plan, and one or more constraints defining restrictions on value combinations assigned to the attributes, wherein the restrictions are Boolean expressions defining whether said value combinations are valid; determining a set of valid value combinations for the attributes that satisfy the restrictions to define the test space for verifying the system behavior; and determining relevant auxiliary variables and a corresponding function for said auxiliary variables to reduce the complexity associated with modeling the test space.

Abstract: Based on a functional coverage by a test suite, a functional coverage model of a System Under Test (SUT) may be defined to represent all covered combinations of functional attributes. Based on an n-wise combination criteria, a subset of the possible combinations of values may be determined A subset of the test suite may be selected such that the selected subset is operative to cover the subset of the determined possible combinations of values. The disclosed subject matter may be used to reduce a size of the test suite while preserving the n-wise combinations coverage of the original test suite.

Abstract: Test coverage is enhanced by measuring various types of coupling between coverage tasks. The coupling measurements may be implicit coupling measurements, explicit coupling measurements, coding coupling measurements, performance coupling measurements, resource coupling measurements or the like. Based on the coupling measurements, different coverage tasks may be grouped together. For example, closely coupled coverage tasks may be grouped together. The groups may also be determined based on an initial distribution of groups, by combining groups having closely coupled member coverage tasks. The groups may be ordered and prioritized, such as based on the size of the groups and the number of uncovered tasks in each group. The groups may also be ordered, such as based on coupling score which aggregate the coupling measurements of the member coverage tasks.

Abstract: Test coverage is enhanced by measuring various types of coupling between coverage tasks. The coupling measurements may be implicit coupling measurements, explicit coupling measurements, coding coupling measurements, performance coupling measurements, resource coupling measurements or the like. Coupling scores are calculated for coverage tasks and based thereon ranking of the coverage tasks or groups of coverage tasks may be determined The ranking may be utilized in selecting for which uncovered coverage task a test should be designed. The ranking may be utilized in computing a coverage measurement of a test suite. The ranking may be utilized to rank tests, based on the coverage tasks each test covers. Ranking of tests may be utilized for various purposes such as performing test selection.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: Detecting optimization opportunities is enabled by utilizing a trace of a target concurrent computer program and determining a relation between data objects accessed during the tracked execution. The relation may be stored in a Temporal Relation Graph (TRG), in an extended-TRG or another data structure. The relation may be affected by temporally-adjacent accesses to data objects. The relation may further be affected by accesses to data objects performed during critical sections of the target program.

Abstract: Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include a state variable AF for one or more states of the target model, wherein AF(S) represents value of the state variable AF at state S; and solving the translated version of the target model that satisfies predetermined constrains.

Abstract: A computer implemented system and method for measuring synchronization coverage for one or more concurrently executed threads is provided. The method comprises updating an identifier of a first thread to comprise an operation identifier associated with a first operation, in response to determining that the first thread has performed the first operation; associating the identifier of the first thread with one or more resources accessed by the first thread; and generating a synchronization coverage model by generating a relational data structure of said one or more resources, wherein a resource is associated with at least the identifier of the first thread and an identifier of a second thread identifier, such that the second thread waits for the first thread before accessing said resource.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: A method for preventing deadlocks in a multiprocessing environment is provided. The method comprises receiving one or more strongly connected components (SCCs) as input, wherein a first SCC represents a set of locks such that each pair of locks in the set may potentially be involved in a deadlock situation; creating a first gate lock for the first SCC, wherein a first process or process element acquires the first gate lock before acquiring a first lock in the first SCC and releases the first gate lock after releasing a number of locks in the first SCC; and removing the first gate lock, in response to determining that the first gate lock introduces new deadlocks.