Patents by Inventor Rachid DAFALI

Rachid DAFALI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Devices and methods for the detection and localization of fault injection attacks
    Patent number: 11930098
    Abstract: A device for detecting perturbation attacks performed on a digital circuit is provided.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: March 12, 2024
    Assignee: SECURE-IC SAS
    Inventor: Rachid Dafali
  • Multi-master security circuit
    Patent number: 11727153
    Abstract: A System on Chip includes at least two hardware masters, a security circuit, and a communication infrastructure for communication between the hardware masters and the security circuit, the communication infrastructure being based on a given interface communication protocol. Each hardware master is configured to send a request to the security circuit for execution of the request by the security circuit through the communication infrastructure, each request comprising at least one service identifier identifying a service.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 15, 2023
    Assignee: SECURE-IC SAS
    Inventors: Rachid Dafali, Freddy David, Michel Le Rolland, Karine Lorvellec
  • DEVICES AND METHODS FOR THE DETECTION AND LOCALIZATION OF FAULT INJECTION ATTACKS
    Publication number: 20220029780
    Abstract: A device for detecting perturbation attacks performed on a digital circuit is provided.
    Type: Application
    Filed: December 20, 2019
    Publication date: January 27, 2022
    Inventor: Rachid DAFALI
  • MULTI-MASTER SECURITY CIRCUIT
    Publication number: 20210312091
    Abstract: A System on Chip includes at least two hardware masters, a security circuit, and a communication infrastructure for communication between the hardware masters and the security circuit, the communication infrastructure being based on a given interface communication protocol. Each hardware master is configured to send a request to the security circuit for execution of the request by the security circuit through the communication infrastructure, each request comprising at least one service identifier identifying a service.
    Type: Application
    Filed: May 24, 2019
    Publication date: October 7, 2021
    Inventors: Rachid DAFALI, Freddy DAVID, Michel LE ROLLAND, Karine LORVELLEC
  • Embedded test circuit for physically unclonable function
    Patent number: 10855476
    Abstract: There is disclosed a silicon integrated circuit comprising a Physically Unclonable Function and an online or embedded test circuit, said online test circuit comprising one or more circuit parts being physically adjacent to said PUF and said one or more circuits embodying one or more tests which can be performed to determine one or more quality properties of said PUF or otherwise characterize it. Different tests with specific associated method steps are described.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: December 1, 2020
    Assignee: SECURE-IC SAS
    Inventors: Rachid Dafali, Jean-Luc Danger, Sylvain Guilley, Florent Lozac'h
  • EMBEDDED TEST CIRCUIT FOR PHYSICALLY UNCLONABLE FUNCTION
    Publication number: 20180183613
    Abstract: There is disclosed a silicon integrated circuit comprising a Physically Unclonable Function and an online or embedded test circuit, said online test circuit comprising one or more circuit parts being physically adjacent to said PUF and said one or more circuits embodying one or more tests which can be performed to determine one or more quality properties of said PUF or otherwise characterize it. Different tests with specific associated method steps are described.
    Type: Application
    Filed: July 1, 2016
    Publication date: June 28, 2018
    Applicant: SECURE-IC SAS
    Inventors: Rachid DAFALI, Jean-Luc DANGER, Sylvain GUILLEY, Florent LOZAC?H