Abstract: Semiconductor optoelectronic devices having a dilute nitride active layer are disclosed. In particular, the semiconductor devices have a dilute nitride active layer with a bandgap within a range from 0.7 eV and 1 eV. Photodetectors comprising a dilute nitride active layer have a responsivity of greater than 0.6 A/W at a wavelength of 1.3 ?m.

Abstract: A VCSEL device having non-coaxial-with-one-another apertures and/or rotationally asymmetric apertures formed in layer(s) of the VCSEL structure to define more than one spatial mode in a light output in operation of the device. An array of such VCSEL devices configured to have different spatial modes at the output of different constituent VCSEL devices. Spatial asymmetry of structure of the constituent VCSEL devices and, therefore, arrays of VCSEL devices causes the overall light output to form an irregular grid of output spots of light. When the VCSEL array is equipped with an appropriate lens array, the spatial components of the light output of the VCSEL array are caused to overlap in the far at the imaging plane in a multiple spatial (and spectral) mode fashion, thereby reducing speckle in imaging applications.

Abstract: A VCSEL device has at least one intracavity contact interleaved with oxidation trenches is disclosed. Interleaving the electrical contacts with the trenches reduces the lateral carrier transport length for current injection associated with the use of an intracavity contact, thereby reducing lateral resistance, while allowing short oxidation times and short oxidation lengths to form the VCSEL confinement structure.

Abstract: Optoelectronic devices having GaInNAsSb, GaInNAsBi or GaInNAsSbBi active layers are disclosed. The optoelectronic devices have an active or absorbing layer, with a bandgap within a range from 0.7 eV and 1.2 eV. The active layer is coupled to a multiplication layer. The multiplication layer is designed to provide a large optical gain with a high signal-to-noise ratio at low light levels at wavelengths up to 1.8 ?m.

Abstract: A stacked superluminescent light-emitting diode having multiple active regions coupled together using and via tunnel junctions. The material compositions of each of the active regions (corresponding quantum wells and/or barriers) differ from one another to provide a controlled different light emission at wavelength (and/or wavelength range) for each junction. In operation of the device, the spectral width of the aggregate light output generated by different junctions is defined by all the junctions, thereby producing a spectrally-broader emission than that of any single, separately taken junction within the device. Thus, the device is configured to operate as a broadband infrared light source.

Abstract: Stacked edge-emitting lasers having multiple active regions coupled together using tunnel junctions. The composition of each of the active regions (quantum wells and/or barriers) differs to provide a controlled different emission wavelength for each junction, when each junction is individually operated at the same fixed temperature. When the device is under operation, a thermal gradient exists across the junctions, and the emission wavelengths of each junction coincide as the different temperature for each junction causes relative wavelength shifts. Thus, the effect of temperature on the emission wavelength of the device is compensated for, producing a narrower linewidth emission.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices having a dilute nitride layer and at least one semiconductor material overlying the dilute nitride layer are disclosed. Hybrid epitaxial growth and the use of aluminum barrier layers to minimize hydrogen diffusion into the dilute nitride layer are used to fabricate high-efficiency multijunction solar cells.

Abstract: Disclosed herein is a laser structure comprising an active region overlying a GaAs substrate. The active region includes a dilute nitride material. The laser is configured to generate light at wavelengths greater than 1300 nm. Also disclosed herein is a photodetector comprising an absorber layer overlying a GaAs substrate. The absorber layer includes a dilute nitride material. The photodetector is configured to detect light at wavelengths greater than 1300 nm. Exemplary dilute nitride materials may include, but are not limited to, GaInNAs and GaInNAsSb. Embodiments of the disclosure may include a dilute nitride-on-GaAs laser structure and a dilute nitride-on-GaAs photodetector.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices having a dilute nitride layer and at least one semiconductor material overlying the dilute nitride layer are disclosed. Hybrid epitaxial growth and the use of aluminum barrier layers to minimize hydrogen diffusion into the dilute nitride layer are used to fabricate high-efficiency multijunction solar cells.

Abstract: Semiconductor optoelectronic devices having a dilute nitride active layer are disclosed. In particular, the semiconductor devices have a dilute nitride active layer with a bandgap within a range from 0.7 eV and 1 eV. Photodetectors comprising a dilute nitride active layer have a responsivity of greater than 0.6 A/W at a wavelength of 1.3 ?m.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices having a dilute nitride layer and at least one semiconductor material overlying the dilute nitride layer are disclosed. Hybrid epitaxial growth and the use of aluminum barrier layers to minimize hydrogen diffusion into the dilute nitride layer are used to fabricate high-efficiency multijunction solar cells.

Abstract: A method of fabricating a layer of single crystal III-N material on a silicon substrate includes epitaxially growing a REO template on a silicon substrate. The template includes a REO layer adjacent the substrate with a crystal lattice spacing substantially matching the crystal lattice spacing of the substrate and selected to protect the substrate from nitridation. Either a rare earth oxynitride or a rare earth nitride is formed adjacent the upper surface of the template and a layer of single crystal III-N material is epitaxially grown thereon.

Abstract: A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.

Abstract: A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.

Abstract: A method of depositing III-V solar collection materials on a GeSn template on a silicon substrate including the steps of providing a crystalline silicon substrate and epitaxially growing a single crystal GeSn layer on the silicon substrate using a grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 ?m to approximately 5 ?m. A layer of III-V solar collection material is epitaxially grown on the graded single crystal GeSn layer. The graded single crystal GeSn layer includes Sn up to an interface with the layer of III-V solar collection material.

Abstract: A method of growing GaN material on a silicon substrate includes providing a single crystal silicon substrate with a (100) surface orientation or a (100) with up to a 10° offset surface orientation and using epi-twist technology, epitaxially growing a single crystal stress managing layer on the silicon substrate. The single crystal stress managing layer includes rare earth oxide with a (110) crystal orientation and a cubic crystal structure. The method further includes epitaxially growing a single crystal buffer layer on the stress managing layer. The single crystal buffer layer includes rare earth oxide with a lattice spacing closer to a lattice spacing of GaN than the rare earth oxide of the stress managing layer. Epitaxially growing a layer of single crystal GaN material on the surface of the buffer, the GaN material having one of a (11-20) crystal orientation and a (0001) crystal orientation.

Abstract: Semiconductor structures are provided comprising a substrate and a epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B; and one or more element selected from the group consisting of Zr, Hf and Al and has a thickness greater than 50 nm. Further, methods for integrating Group III nitrides onto a substrate comprising, forming an epitaxial buffer layer of a diboride of Zr, Hf, Al, or mixtures thereof, over a substrate; and forming a Group III nitride layer over the buffer layer, are provided which serve to thermally decouple the buffer layer from the underlying substrate, thereby greatly reducing the strain induced in the semiconductor structures upon fabrication and/or operation.

Abstract: A method of forming a template on a silicon substrate includes the step of providing a single crystal silicon substrate having a protective layer of amorphous silicon oxide on an upper surface thereof. A working area is delineated on the upper surface of the silicon substrate and a rare earth metal oxide is formed on the upper surface of the silicon substrate within the working area. The rare earth metal oxide is crystal lattice matched to the upper surface of the silicon substrate to form a template for further operations and portions of the upper surface outside the working area are covered with the protective layer of amorphous silicon oxide.

Abstract: A photonic structure including a substrate of either crystalline silicon or germanium and a multilayer distributed Bragg reflector (DBR) positioned on the substrate. The DBR includes material substantially crystal lattice matching the DBR to the substrate. The DBR includes a plurality of pairs of layers of material including any combination of IV materials and any rare earth oxide (REO). A photonic device including multilayers of single crystal IV material positioned on the DBR and including material substantially crystal lattice matching the DBR to the photonic device.

Abstract: An electronic device includes IV material grown on a silicon substrate. The device includes a crystalline silicon substrate and a rare earth structure epitaxially grown on the silicon substrate. The rare earth structure includes a layer of a rare earth oxide with electrical insulating characteristics so that the rare earth structure provides electrical insulation from the silicon substrate. A single crystal IV material film is epitaxially grown on the rare earth structure. The single crystal IV material film includes one of crystal lattice matching or crystal lattice mismatching the IV material film to the rare earth structure.