Patents by Inventor Radek Roucka

Radek Roucka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190013429
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices having a dilute nitride layer and at least one semiconductor material overlying the dilute nitride layer are disclosed. Hybrid epitaxial growth and the use of aluminum barrier layers to minimize hydrogen diffusion into the dilute nitride layer are used to fabricate high-efficiency multijunction solar cells.
    Type: Application
    Filed: June 26, 2018
    Publication date: January 10, 2019
    Inventors: FERRAN SUAREZ, TING LIU, ARSEN SUKIASYAN, IVAN HERNANDEZ, JORDAN LANG, RADEK ROUCKA, SABEUR SIALA, AYMERIC MAROS
  • Patent number: 9496132
    Abstract: A method of fabricating a layer of single crystal III-N material on a silicon substrate includes epitaxially growing a REO template on a silicon substrate. The template includes a REO layer adjacent the substrate with a crystal lattice spacing substantially matching the crystal lattice spacing of the substrate and selected to protect the substrate from nitridation. Either a rare earth oxynitride or a rare earth nitride is formed adjacent the upper surface of the template and a layer of single crystal III-N material is epitaxially grown thereon.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: November 15, 2016
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Andrew Clark, Rytis Dargis, Radek Roucka, Michael Lebby
  • Patent number: 9443939
    Abstract: A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: September 13, 2016
    Assignee: Translucent, Inc.
    Inventors: Rytis Dargis, Erdem Arkun, Radek Roucka, Andrew Clark, Michael Lebby
  • Publication number: 20160133708
    Abstract: A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
    Type: Application
    Filed: October 27, 2015
    Publication date: May 12, 2016
    Inventors: Rytis Dargis, Erdem Arkun, Radek Roucka, Andrew Clark, Michael Lebby
  • Patent number: 8889978
    Abstract: A method of depositing III-V solar collection materials on a GeSn template on a silicon substrate including the steps of providing a crystalline silicon substrate and epitaxially growing a single crystal GeSn layer on the silicon substrate using a grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 ?m to approximately 5 ?m. A layer of III-V solar collection material is epitaxially grown on the graded single crystal GeSn layer. The graded single crystal GeSn layer includes Sn up to an interface with the layer of III-V solar collection material.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 18, 2014
    Assignee: Translucent, Inc.
    Inventors: Radek Roucka, Michael Lebby, Scott Semans
  • Patent number: 8846504
    Abstract: A method of growing GaN material on a silicon substrate includes providing a single crystal silicon substrate with a (100) surface orientation or a (100) with up to a 10° offset surface orientation and using epi-twist technology, epitaxially growing a single crystal stress managing layer on the silicon substrate. The single crystal stress managing layer includes rare earth oxide with a (110) crystal orientation and a cubic crystal structure. The method further includes epitaxially growing a single crystal buffer layer on the stress managing layer. The single crystal buffer layer includes rare earth oxide with a lattice spacing closer to a lattice spacing of GaN than the rare earth oxide of the stress managing layer. Epitaxially growing a layer of single crystal GaN material on the surface of the buffer, the GaN material having one of a (11-20) crystal orientation and a (0001) crystal orientation.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: September 30, 2014
    Assignee: Translucent, Inc.
    Inventors: Rytis Dargis, Andrew Clark, Erdem Arkun, Radek Roucka
  • Patent number: 8803194
    Abstract: Semiconductor structures are provided comprising a substrate and a epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B; and one or more element selected from the group consisting of Zr, Hf and Al and has a thickness greater than 50 nm. Further, methods for integrating Group III nitrides onto a substrate comprising, forming an epitaxial buffer layer of a diboride of Zr, Hf, Al, or mixtures thereof, over a substrate; and forming a Group III nitride layer over the buffer layer, are provided which serve to thermally decouple the buffer layer from the underlying substrate, thereby greatly reducing the strain induced in the semiconductor structures upon fabrication and/or operation.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: August 12, 2014
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona Acting for and on Behalf of Arizona State University
    Inventors: John Kouvetakis, Radek Roucka
  • Patent number: 8679953
    Abstract: A method of forming a template on a silicon substrate includes the step of providing a single crystal silicon substrate having a protective layer of amorphous silicon oxide on an upper surface thereof. A working area is delineated on the upper surface of the silicon substrate and a rare earth metal oxide is formed on the upper surface of the silicon substrate within the working area. The rare earth metal oxide is crystal lattice matched to the upper surface of the silicon substrate to form a template for further operations and portions of the upper surface outside the working area are covered with the protective layer of amorphous silicon oxide.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: March 25, 2014
    Assignee: Translucent, Inc.
    Inventors: Andrew Clark, Erdem Arkun, Radek Roucka
  • Publication number: 20140077240
    Abstract: A photonic structure including a substrate of either crystalline silicon or germanium and a multilayer distributed Bragg reflector (DBR) positioned on the substrate. The DBR includes material substantially crystal lattice matching the DBR to the substrate. The DBR includes a plurality of pairs of layers of material including any combination of IV materials and any rare earth oxide (REO). A photonic device including multilayers of single crystal IV material positioned on the DBR and including material substantially crystal lattice matching the DBR to the photonic device.
    Type: Application
    Filed: September 17, 2012
    Publication date: March 20, 2014
    Inventors: Radek Roucka, Michael Lebby, Scott Semans, Andrew Clark
  • Publication number: 20140077339
    Abstract: A IV or III-V device is fabricated on a germanium template on a silicon substrate and includes a thin layer of Ge epitaxially grown on a silicon substrate. The thin layer includes Ge delta doped with Sn at the silicon substrate. A single crystal layer of Ge is epitaxially grown on the thin layer of Ge doped with Sn. A structure including one of IV material and III-V material is epitaxially grown on the single crystal layer of Ge.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Inventors: Radek Roucka, Michael Lebby, Scott Semans
  • Publication number: 20140077338
    Abstract: An electronic device includes IV material grown on a silicon substrate. The device includes a crystalline silicon substrate and a rare earth structure epitaxially grown on the silicon substrate. The rare earth structure includes a layer of a rare earth oxide with electrical insulating characteristics so that the rare earth structure provides electrical insulation from the silicon substrate. A single crystal IV material film is epitaxially grown on the rare earth structure. The single crystal IV material film includes one of crystal lattice matching or crystal lattice mismatching the IV material film to the rare earth structure.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Inventors: Radek Roucka, Michael Lebby, Scott Semans
  • Publication number: 20140076390
    Abstract: A method of depositing III-V solar collection materials on a GeSn template on a silicon substrate including the steps of providing a crystalline silicon substrate and epitaxially growing a single crystal GeSn layer on the silicon substrate using a grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 ?m to approximately 5 ?m. A layer of III-V solar collection material is epitaxially grown on the graded single crystal GeSn layer. The graded single crystal GeSn layer includes Sn up to an interface with the layer of III-V solar collection material.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Inventors: Radek Roucka, Michael Lebby, Scott Semans
  • Publication number: 20140053894
    Abstract: A method of fabricating a solar cell on a silicon substrate includes providing a crystalline silicon substrate, selecting a grading profile, epitaxially growing a template on the silicon substrate including a single crystal GeSn layer using the grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 ?m to approximately 5 ?m. At least two layers of high band gap material are epitaxially and sequentially grown on the template to form at least three junctions. The grading profile starts with the Sn at or near zero with the Ge at zero, the percentage of Sn varies to a maximum mid-area, and reduces the percentage of Sn to zero adjacent an upper surface.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Inventors: Radek Roucka, Michael Lebby, Scott Semans
  • Publication number: 20130313579
    Abstract: Detectors based on such Ge(Sn) alloys of the formula Ge1-xSnx (e.g., 0<x<0.01) have increased responsivity while keeping alloy scattering to a minimum. Such small amounts of Sn are also useful for improving the performance of the recently demonstrated Ge-on-Si laser structures, since the addition of Sn monotonically reduces the separation between the direct and indirect minima in the conduction band of Ge. Thus, provided herein are Ge(Sn) alloys of the formula Ge1xSnx, wherein x is less than 0.01, wherein the alloy is optionally n-doped or p-doped; and assemblies and photodiodes comprising the same, and methods for their formation.
    Type: Application
    Filed: November 18, 2011
    Publication date: November 28, 2013
    Inventors: John Kouvetakis, Richard Beeler, Jose Menendez, Radek Roucka
  • Patent number: 8545627
    Abstract: Semiconductor structures are provided comprising a substrate and a epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B; and one or more element selected from the group consisting of Zr, Hf and Al and has a thickness greater than 50 nm. Further, methods for integrating Group III nitrides onto a substrate comprising, forming an epitaxial buffer layer of a diboride of Zr, Hf, Al, or mixtures thereof, over a substrate; and forming a Group III nitride layer over the buffer layer, are provided which serve to thermally decouple the buffer layer from the underlying substrate, thereby greatly reducing the strain induced in the semiconductor structures upon fabrication and/or operation.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: October 1, 2013
    Assignee: Arizona Board of Regents
    Inventors: John Kouvetakis, Radek Roucka
  • Publication number: 20130248853
    Abstract: A method of fabricating a layer of single crystal III-N material on a silicon substrate includes epitaxially growing a REO template on a silicon substrate. The template includes a REO layer adjacent the substrate with a crystal lattice spacing substantially matching the crystal lattice spacing of the substrate and selected to protect the substrate from nitridation. Either a rare earth oxynitride or a rare earth nitride is formed adjacent the upper surface of the template and a layer of single crystal III-N material is epitaxially grown thereon.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 26, 2013
    Inventors: Erdem Arkun, Andrew Clark, Rytis Dargis, Radek Roucka, Michael Lebby
  • Publication number: 20130214282
    Abstract: A method of fabricating a layer of single crystal semiconductor material on a silicon substrate including providing a crystalline silicon substrate and epitaxially depositing a nano structured interface layer on the substrate. The nano structured interface layer has a thickness up to a critical thickness. The method further includes epitaxially depositing a layer of single crystal semiconductor material in overlying relationship to the nano structured interface layer. Preferably, the method includes the nano structured interface layer being a layer of coherently strained nano dots of selected material. The critical thickness of the nano dots includes a thickness up to a thickness at which the nano dots become incoherent.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 22, 2013
    Inventors: Erdem Arkun, Radek Roucka, Andrew Clark, Robin Smith, Michael Lebby
  • Publication number: 20130099357
    Abstract: A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Inventors: Rytis Dargis, Erdem Arkun, Radek Roucka, Andrew Clark, Michael Lebby
  • Publication number: 20120025212
    Abstract: Photodiode devices with GeSn active layers can be integrated directly on p+ Si platforms under CMOS-compatible conditions. It has been found that even minor amounts of Sn incorporation (2%) dramatically expand the range of IR detection up to at least 1750 nm and substantially increases the absorption. The corresponding photoresponse can cover of all telecommunication bands using entirely group IV materials.
    Type: Application
    Filed: September 16, 2009
    Publication date: February 2, 2012
    Applicant: Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University
    Inventors: John Kouvetakis, Jose Menendez, Radek Roucka, Jay Mathews
  • Patent number: 8029905
    Abstract: The present invention provides novel compounds of the formula Gei-x-ySixSny, wherein 0.01<y<0.11, and 0.26<x<0.35, and semiconductor structures comprising such compounds. The present invention also provides novel semiconductor structures comprising silicon substrates, an SiGe buffer layer, and a Group III-V or II-VI active layer. The present invention also provides novel semiconductor structures comprising silicon substrates, an SiGe buffer layer, an SiGeSn template layer, and an SiGe, Ge, Group III-V, or Group II-VI active layer.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: October 4, 2011
    Assignee: Arizona Board of Regents, a Body Corporate of the State of Arizona acting for and on behalf of Arizona State University
    Inventors: John Kouvetakis, Radek Roucka