Abstract: A hierarchical approach is provided to integrate functions and components into the various systems and subsystems within a distribution network, including standardization of modular and scalable power electronics power blocks with embedded diagnostics and prognostics.

Abstract: A hierarchical approach is provided to integrate functions and components into the various systems and subsystems within a distribution network, including standardization of modular and scalable power electronics power blocks with embedded diagnostics and prognostics.

Abstract: A hierarchical approach is provided to integrate functions and components into the various systems and subsystems within a distribution network, including standardization of modular and scalable power electronics power blocks with embedded diagnostics and prognostics.

Abstract: A hierarchical approach is provided to integrate functions and components into the various systems and subsystems within a distribution network, including standardization of modular and scalable power electronics power blocks with embedded diagnostics and prognostics.

Abstract: A Functional Safety Timer (FST) and method of for monitoring functional safety in Integrated Circuits (ICs) is disclosed. The FST includes hardware based counter for counting programmed number of cycles associated with an event of peripheral device. The FST includes first logic circuit and second logic circuit. The first logic circuit receives first trigger of peripheral device. In response to first trigger, the counter is initiated by first logic circuit. The second logic circuit receives second trigger of peripheral device. In response to second trigger, the counter being initiated is terminated by the second logic circuit. Further, the FST includes a hardware based comparator for comparing the number of cycles counted by the hardware based counter with a threshold time associated with the event and a plurality of programmable registers for determining one or more faults associated with the event based on result of the comparison and sequence of events.

Abstract: A Functional Safety Timer (FST) and method of for monitoring functional safety in Integrated Circuits (ICs) is disclosed. The FST includes hardware based counter for counting programmed number of cycles associated with an event of peripheral device. The FST includes first logic circuit and second logic circuit. The first logic circuit receives first trigger of peripheral device. In response to first trigger, the counter is initiated by first logic circuit. The second logic circuit receives second trigger of peripheral device. In response to second trigger, the counter being initiated is terminated by the second logic circuit. Further, the FST includes a hardware based comparator for comparing the number of cycles counted by the hardware based counter with a threshold time associated with the event and a plurality of programmable registers for determining one or more faults associated with the event based on result of the comparison and sequence of events.

Abstract: The present disclosure relates to a method for dynamically optimizing power consumption in a System-on-Chip (SoC). The method comprises receiving at least one interrupt signal from a peripheral controller. The method further comprises switching clock frequency of the peripheral controller to a lower clock frequency than a normal operating clock frequency upon receiving the at least one interrupt. The method further comprises providing the lower clock frequency than the normal operating clock frequency to the peripheral controller for dynamically optimizing the power consumption of the SoC.

Abstract: This disclosure relates generally to methods and systems for reducing complexity of synthesis and static timing analysis (STA) part in SoC design arising out of designs received from multiple sources of IC blocks. In one embodiment, an integrated circuit design apparatus is provided. The apparatus comprises one or more hardware processors and one or more memory units storing instructions executable by the one or more hardware processors for obtaining register transfer level code for an integrated circuit design block; parsing the register transfer level code to extract a pragma included in the register transfer level code for the integrated design block; determining a timing constraint from the extracted pragma; synthesizing a netlist for an integrated circuit design including at least one instance of the integrated circuit design block, using the determined timing constraint; and providing the netlist for use in an integrated circuit manufacturing process.

Abstract: The present disclosure presents method and unit for handling interrupts in a system. The method comprises receiving, by a receiving module of a Withdrawal Reflex Unit (WRU), one or more interrupt requests from one or more peripheral devices of a system, providing, by an action register of the WRU, one or more outputs to a control logic circuit of the WRU, based on the one or more interrupt requests, enabling, by the control logic circuit, at least one output port of the WRU based on the one or more outputs, where the one or more peripheral devices and one or more components of the system are connected to the at least one output port to perform one or more actions and generating, by a status register of the WRU, an indication of the one or more actions performed to handle the one or more interrupt requests to take immediate action.

Abstract: The present disclosure relates to a method for dynamically optimizing power consumption in a System-on-Chip (SoC). The method comprises receiving at least one interrupt signal from a peripheral controller. The method further comprises switching clock frequency of the peripheral controller to a lower clock frequency than a normal operating clock frequency upon receiving the at least one interrupt. The method further comprises providing the lower clock frequency than the normal operating clock frequency to the peripheral controller for dynamically optimizing the power consumption of the SoC.